From patchwork Tue Mar 15 17:30:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwendal Grignou X-Patchwork-Id: 552010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EB42C4167E for ; Tue, 15 Mar 2022 17:31:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350595AbiCORcM (ORCPT ); Tue, 15 Mar 2022 13:32:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350610AbiCORcK (ORCPT ); Tue, 15 Mar 2022 13:32:10 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 217C35882A for ; Tue, 15 Mar 2022 10:30:58 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id t5so103915pfg.4 for ; Tue, 15 Mar 2022 10:30:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OVHw4FMRix6/1vFaeCXhjJBzU9T7lPDEf8vcs78GDek=; b=bQTHUgEZuecTqo2HHUqWYxkppCFWk077qgGs2z6U/kCBfqjYgF4e3WeNmEm2eh34sT QWzAeXPlOyM7GiKKU22Znwk4GjvfD/95jLVOkNJCm8sxzQvFJ6+xDVYEm1N+CC8p38Xe ZtLEV3pHp3XpTUY92AqzUfTxfD6Jk37xzr/rw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OVHw4FMRix6/1vFaeCXhjJBzU9T7lPDEf8vcs78GDek=; b=dYrz3Aidimg4CEVD9P3VUNXEtmGSJ1kfSvF5iO58tT9iDuMUmGUaogFipehHh7VjnW ldhz4IIbkcV6Bt0mPs1NlSW6fMsY4PPJTg0z6PNSG++Rd8R5hQlmBjgbGEmEss2/ts17 SLWRt70iFl4zOWRdqW+3k+K1Dog3OFfow8W4H7PuPOFs4T/jvHyCk5A8htraT2lSoTEe JwJ7TgH17gPvAKgqq3I/pha1iZzV7BUbo+O10uM3/PzF4Op5VGXAdg6B6L4znndYAbLt cZ3NHYTy7fMnNwz/leAbokCXB0ErkmvYwc0XMISyJQOstIl80de+kap26yq99wpMyEVq 53HQ== X-Gm-Message-State: AOAM531GFguHRrEY/sC9HX0E5UGvvX0AH7SzbnSmhbh4pC63fNyZk/LR 6YzaMQs1VDkKxhNvy9q537kmCQ== X-Google-Smtp-Source: ABdhPJyfEKc72dblYHJJuQRpa94C75jiedZC3nP6P8uFSy9tXkVO68uAH8xu9Tu+Q2m8HTTTOuYIaw== X-Received: by 2002:a65:494b:0:b0:380:6517:cb32 with SMTP id q11-20020a65494b000000b003806517cb32mr25593619pgs.145.1647365457428; Tue, 15 Mar 2022 10:30:57 -0700 (PDT) Received: from localhost ([2620:15c:202:201:53f9:5c35:428f:83a1]) by smtp.gmail.com with UTF8SMTPSA id s14-20020a056a0008ce00b004f66dcd4f1csm27389706pfu.32.2022.03.15.10.30.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Mar 2022 10:30:57 -0700 (PDT) From: Gwendal Grignou To: jic23@kernel.org, robh+dt@kernel.org, swboyd@chromium.org Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Gwendal Grignou Subject: [PATCH 3/7] iio: sx9324: Add precharge internal resistance setting Date: Tue, 15 Mar 2022 10:30:38 -0700 Message-Id: <20220315173042.1325858-4-gwendal@chromium.org> X-Mailer: git-send-email 2.35.1.723.g4982287a31-goog In-Reply-To: <20220315173042.1325858-1-gwendal@chromium.org> References: <20220315173042.1325858-1-gwendal@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add ability to set the precharge internal resistance from the device tree. Signed-off-by: Gwendal Grignou --- drivers/iio/proximity/sx9324.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/iio/proximity/sx9324.c b/drivers/iio/proximity/sx9324.c index 1bef16437aa84..785af857b23a1 100644 --- a/drivers/iio/proximity/sx9324.c +++ b/drivers/iio/proximity/sx9324.c @@ -70,7 +70,8 @@ #define SX9324_REG_AFE_PH2 0x2a #define SX9324_REG_AFE_PH3 0x2b #define SX9324_REG_AFE_CTRL8 0x2c -#define SX9324_REG_AFE_CTRL8_RESFILTN_4KOHM 0x02 +#define SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM 0x02 +#define SX9324_REG_AFE_CTRL8_RESFILTIN_MASK GENMASK(3, 0) #define SX9324_REG_AFE_CTRL9 0x2d #define SX9324_REG_AFE_CTRL9_AGAIN_1 0x08 @@ -781,7 +782,7 @@ static const struct sx_common_reg_default sx9324_default_regs[] = { { SX9324_REG_AFE_PH2, 0x1a }, { SX9324_REG_AFE_PH3, 0x16 }, - { SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESFILTN_4KOHM }, + { SX9324_REG_AFE_CTRL8, 0x10 | SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM }, { SX9324_REG_AFE_CTRL9, SX9324_REG_AFE_CTRL9_AGAIN_1 }, { SX9324_REG_PROX_CTRL0, SX9324_REG_PROX_CTRL0_GAIN_1 | @@ -891,6 +892,15 @@ sx9324_get_default_reg(struct device *dev, int idx, reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL4_RESOLUTION_MASK, raw); break; + case SX9324_REG_AFE_CTRL8: + ret = device_property_read_u32(dev, + "semtech,input-precharge-resistor", + &raw); + reg_def->def &= ~SX9324_REG_AFE_CTRL8_RESFILTIN_MASK; + reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL8_RESFILTIN_MASK, + raw / 2); + break; + case SX9324_REG_ADV_CTRL5: ret = device_property_read_u32(dev, "semtech,startup-sensor", &start);