From patchwork Tue Mar 15 14:26:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 552023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02247C43219 for ; Tue, 15 Mar 2022 14:26:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349049AbiCOO2H (ORCPT ); Tue, 15 Mar 2022 10:28:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349050AbiCOO2F (ORCPT ); Tue, 15 Mar 2022 10:28:05 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 50FA154BF0; Tue, 15 Mar 2022 07:26:53 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.90,183,1643641200"; d="scan'208";a="113582328" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 15 Mar 2022 23:26:52 +0900 Received: from localhost.localdomain (unknown [10.226.92.209]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8348E439248A; Tue, 15 Mar 2022 23:26:50 +0900 (JST) From: Biju Das To: Rob Herring Cc: Biju Das , Geert Uytterhoeven , Lad Prabhakar , devicetree@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Date: Tue, 15 Mar 2022 14:26:38 +0000 Message-Id: <20220315142644.17660-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220315142644.17660-1-biju.das.jz@bp.renesas.com> References: <20220315142644.17660-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's. SYSC controller found on the RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55 core0 reset vector address configuration register. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Rob Herring --- v2->v3: * Changed the compatible from r9a07g043u-sysc->r9a07g043-sysc * Retained Rb tag from Rob as it is trivial change. V1->V2: * No change --- .../devicetree/bindings/power/renesas,rzg2l-sysc.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml index bb433e75a0ee..9ccc23ae7054 100644 --- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml @@ -10,8 +10,8 @@ maintainers: - Geert Uytterhoeven description: - The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI - and supports following functions, + The RZ/{G2L,V2L}-alike System Controller (SYSC) performs system control of + the LSI and supports following functions, - External terminal state capture function - 34-bit address space access function - Low power consumption control @@ -20,8 +20,9 @@ description: properties: compatible: enum: - - renesas,r9a07g044-sysc # RZ/G2{L,LC} - - renesas,r9a07g054-sysc # RZ/V2L + - renesas,r9a07g043-sysc # RZ/G2UL + - renesas,r9a07g044-sysc # RZ/G2{L,LC} + - renesas,r9a07g054-sysc # RZ/V2L reg: maxItems: 1