From patchwork Tue Mar 8 19:08:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 549423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2652BC433FE for ; Tue, 8 Mar 2022 19:09:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349868AbiCHTKP (ORCPT ); Tue, 8 Mar 2022 14:10:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349874AbiCHTKO (ORCPT ); Tue, 8 Mar 2022 14:10:14 -0500 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FFB648E53 for ; Tue, 8 Mar 2022 11:09:16 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id n15so7954759plh.2 for ; Tue, 08 Mar 2022 11:09:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TukPsTakLeJLLpOHxj5U6zbUOX+HpPNC5juckJdtkGc=; b=bG90AlQ35R976HVEt3EiNjnAAZRltYCer7lgVDl2CBxgHxRHT0U5M9YdzxVk2mmKI9 uQHr+VZU3Zt9PDWsu7fFhhs3KzeXXsSJ5i7iH7lu/27aopmKU8nL5QrBZ6E1jcyH5fnY aNd4uJJJKIWzW744O3mt/ZSmLh6igdfg7V/IA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TukPsTakLeJLLpOHxj5U6zbUOX+HpPNC5juckJdtkGc=; b=CVUjvOmSDGGUPVQ6cYynwbnJ6WBDHAkrDq50yHuOYhB35j3yNs6jkyoRb592xj2fiF BQXjXVWKg34wcKRqO57YZ6JFcCIfCglKsx0hO13ZaxaN8Ek8a7X+eUkqFc9dPz+fVNPl DUInWtBxkalKy2TjP85SgRNKfIPsICvFhNqt7yKsa4UJk2CXOkpfHqzL0llriihvowOw AEwVOQK4QxvT7jbXH3eWTydyUpzjvp59LJgQ78Jr/wiiNPcyMfvkR1+Nzp5IC44xdXsR MwFdsKI8XFYZ4Oq4YBE9rVjAL1b+qHfjxJFtV8CNWY/CbqqM89f1Zf7VfdkJc9uU7RlW reNA== X-Gm-Message-State: AOAM532GqQ4FeUxzuEEw4MI4YywMFqRsi0bfIAFpZOzP1vZcyD7jB8TD oocP+yFeRKaIrQLNSVk1/9+BFw== X-Google-Smtp-Source: ABdhPJykCBYHNRLZLOxaBgcOcb+HYAE6UHeIN2/NgAuMxlP9SyrFIHZjXykkIWIaxv9ICBnq57ZimQ== X-Received: by 2002:a17:902:dad2:b0:151:f895:9c31 with SMTP id q18-20020a170902dad200b00151f8959c31mr7535212plx.93.1646766556509; Tue, 08 Mar 2022 11:09:16 -0800 (PST) Received: from localhost ([2620:15c:202:201:b3e3:a188:cbfc:3a0e]) by smtp.gmail.com with UTF8SMTPSA id d7-20020a056a00244700b004e1300a2f7csm20703284pfj.212.2022.03.08.11.09.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Mar 2022 11:09:16 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Brian Norris , Rob Herring , Krzysztof Kozlowski Subject: [PATCH v4 03/15] dt-bindings: devfreq: rk3399_dmc: Fix Hz units Date: Tue, 8 Mar 2022 11:08:49 -0800 Message-Id: <20220308110825.v4.3.I9341269171c114d0e04e41d48037fd32816e2d8c@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The driver and all downstream device trees [1] are using Hz units, but the document claims MHz. DRAM frequency for these systems can't possibly exceed 2^32-1 Hz, so the choice of unit doesn't really matter than much. Rather than add unnecessary risk in getting the units wrong, let's just go with the unofficial convention and make the docs match reality. A sub-1MHz frequency is extremely unlikely, so include a minimum in the schema, to help catch anybody who might have believed this was MHz. [1] And notably, also those trying to upstream them: https://lore.kernel.org/lkml/20210308233858.24741-3-daniel.lezcano@linaro.org/ Signed-off-by: Brian Norris Reviewed-by: Rob Herring Acked-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- (no changes since v3) Changes in v3: * Add Reviewed-by, Acked-by .../rockchip,rk3399-dmc.yaml | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml index 356bbe5db383..96efb23cfc0f 100644 --- a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml @@ -115,11 +115,11 @@ properties: rockchip,ddr3_odt_dis_freq: $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1000000 # In case anyone thought this was MHz. description: When the DRAM type is DDR3, this parameter defines the ODT disable - frequency in MHz (Mega Hz). When the DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both - disabled. + frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq, + the ODT on the DRAM side and controller side are both disabled. rockchip,ddr3_drv: deprecated: true @@ -163,11 +163,11 @@ properties: rockchip,lpddr3_odt_dis_freq: $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1000000 # In case anyone thought this was MHz. description: When the DRAM type is LPDDR3, this parameter defines then ODT disable - frequency in MHz (Mega Hz). When DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both - disabled. + frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the + ODT on the DRAM side and controller side are both disabled. rockchip,lpddr3_drv: deprecated: true @@ -210,11 +210,11 @@ properties: rockchip,lpddr4_odt_dis_freq: $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1000000 # In case anyone thought this was MHz. description: When the DRAM type is LPDDR4, this parameter defines the ODT disable - frequency in MHz (Mega Hz). When the DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both - disabled. + frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq, + the ODT on the DRAM side and controller side are both disabled. rockchip,lpddr4_drv: deprecated: true @@ -300,7 +300,7 @@ examples: rockchip,sr_mc_gate_idle = <0x3>; rockchip,srpd_lite_idle = <0x4>; rockchip,standby_idle = <0x2000>; - rockchip,ddr3_odt_dis_freq = <333>; - rockchip,lpddr3_odt_dis_freq = <333>; - rockchip,lpddr4_odt_dis_freq = <333>; + rockchip,ddr3_odt_dis_freq = <333000000>; + rockchip,lpddr3_odt_dis_freq = <333000000>; + rockchip,lpddr4_odt_dis_freq = <333000000>; };