From patchwork Mon Mar 7 14:34:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 548961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0FA3C433EF for ; Mon, 7 Mar 2022 14:34:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243267AbiCGOfk (ORCPT ); Mon, 7 Mar 2022 09:35:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243260AbiCGOfj (ORCPT ); Mon, 7 Mar 2022 09:35:39 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 39C087D02C; Mon, 7 Mar 2022 06:34:45 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 088861042; Mon, 7 Mar 2022 06:34:45 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0B3633F66F; Mon, 7 Mar 2022 06:34:42 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Rob Herring , Mesih Kilinc , Icenowy Zheng , Jesse Taube , Giulio Benetti , George Hilliard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Ulf Hansson , linux-mmc@vger.kernel.org Subject: [PATCH 08/14] ARM: dts: suniv: F1C100: add MMC controllers Date: Mon, 7 Mar 2022 14:34:15 +0000 Message-Id: <20220307143421.1106209-9-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307143421.1106209-1-andre.przywara@arm.com> References: <20220307143421.1106209-1-andre.przywara@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jesse Taube The F1C100 series contains two MMC controllers, where the first one is typically connected to an (micro)SD card slot (as this is the one the BROM is able to boot from). Describe the two controllers in the SoC .dtsi. We also add the pinctrl description for MMC0, since this is the only pin set supporting that function anyway, and SD cards are very common across boards. Signed-off-by: Jesse Taube Signed-off-by: Andre Przywara --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 57f8932ef898..6f2f97458fe0 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -69,6 +69,42 @@ otg_sram: sram-section@0 { }; }; + mmc0: mmc@1c0f000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <23>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <24>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ccu: clock@1c20000 { compatible = "allwinner,suniv-f1c100s-ccu"; reg = <0x01c20000 0x400>; @@ -96,6 +132,12 @@ pio: pinctrl@1c20800 { #interrupt-cells = <3>; #gpio-cells = <3>; + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + }; + uart0_pe_pins: uart0-pe-pins { pins = "PE0", "PE1"; function = "uart0";