From patchwork Mon Mar 7 11:31:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sanil, Shruthi" X-Patchwork-Id: 548991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F942C433FE for ; Mon, 7 Mar 2022 11:33:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234772AbiCGLeC (ORCPT ); Mon, 7 Mar 2022 06:34:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240972AbiCGLdt (ORCPT ); Mon, 7 Mar 2022 06:33:49 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34A0EC07; Mon, 7 Mar 2022 03:31:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646652715; x=1678188715; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=cx3ne0GM/fbTd3gNnz8RFI9E54C9dp2Ly8Gey+pcpSs=; b=Te1u32JhRUEn6gZfCWjdDymlFVhlkHNjBd8CCYUGMYnXGC62DEPt4Ypp IlwIiwxUJY1rYAnq1Lvv1J1pSkJLLMbcvPn8VED1Uf0hihaUoJVi20bjB 8lxRoYw1XetJv7Q6IZU0phFbhWY/RQMwJmHdxeMdx9eo/K+wSGaNm8zMr E0je3GbCL1xfQJasAdOEbgjqECe+2+pNeRabnDuEmChfAvq0z0TeRn1Jh S252vJfUTT/ivsLoduULAd+RmhLrDFIEZmuBCnnZ1z7EfVWMNbXj6OXLS 0cqEr6ClR8EOLm42kAx80X4ZeYXNymDOGTCKOwupNO+b7Q50SzLnZyIz8 g==; X-IronPort-AV: E=McAfee;i="6200,9189,10278"; a="234324460" X-IronPort-AV: E=Sophos;i="5.90,162,1643702400"; d="scan'208";a="234324460" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 03:31:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,162,1643702400"; d="scan'208";a="643212676" Received: from gio-01395267462.iind.intel.com ([10.49.4.124]) by orsmga004.jf.intel.com with ESMTP; 07 Mar 2022 03:31:51 -0800 From: shruthi.sanil@intel.com To: daniel.lezcano@linaro.org, tglx@linutronix.de, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: andriy.shevchenko@linux.intel.com, mgross@linux.intel.com, srikanth.thokala@intel.com, lakshmi.bai.raja.subramanian@intel.com, mallikarjunappa.sangannavar@intel.com, shruthi.sanil@intel.com Subject: [PATCH v9 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer Date: Mon, 7 Mar 2022 17:01:46 +0530 Message-Id: <20220307113147.19496-2-shruthi.sanil@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220307113147.19496-1-shruthi.sanil@intel.com> References: <20220307113147.19496-1-shruthi.sanil@intel.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Shruthi Sanil Add Device Tree bindings for the Timer IP, which can be used as clocksource and clockevent device in the Intel Keem Bay SoC. Reviewed-by: Andy Shevchenko Signed-off-by: Shruthi Sanil --- .../bindings/timer/intel,keembay-timer.yaml | 125 ++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml new file mode 100644 index 000000000000..333f137e39e0 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay SoC Timers + +maintainers: + - Shruthi Sanil + +description: | + The Intel Keem Bay timer IP supports 1 free running counter and 8 timers. + Each timer is capable of generating inividual interrupt. + Both the features are enabled through the timer general config register. + + The parent node represents the common general configuration details and + the child nodes represents the counter and timers. + +properties: + compatible: + items: + - enum: + - intel,keembay-gpt-creg + - const: simple-mfd + + reg: + description: General configuration register address and length. + maxItems: 1 + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +required: + - compatible + - reg + - ranges + - "#address-cells" + - "#size-cells" + +patternProperties: + "^counter@[0-9a-f]+$": + description: Properties for Intel Keem Bay counter. + type: object + properties: + compatible: + items: + - enum: + - intel,keembay-counter + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + required: + - compatible + - reg + - clocks + + "^timer@[0-9a-f]+$": + description: Properties for Intel Keem Bay timer + type: object + properties: + compatible: + items: + - enum: + - intel,keembay-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + #define KEEM_BAY_A53_TIM + + soc { + #address-cells = <0x2>; + #size-cells = <0x2>; + + gpt@20331000 { + compatible = "intel,keembay-gpt-creg", "simple-mfd"; + reg = <0x0 0x20331000 0x0 0xc>; + ranges = <0x0 0x0 0x20330000 0xF0>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + counter@e8 { + compatible = "intel,keembay-counter"; + reg = <0xe8 0x8>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@30 { + compatible = "intel,keembay-timer"; + reg = <0x30 0xc>; + interrupts = ; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + }; + }; + +...