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Fri, 4 Mar 2022 21:11:20 -0800 Envelope-to: dwmw2@infradead.org, yilun.xu@intel.com, mdf@kernel.org, robh@kernel.org, trix@redhat.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Received: from [172.19.72.93] (port=44412 helo=xsj-xw9400.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1nQMhM-000GqD-Iy; Fri, 04 Mar 2022 21:11:20 -0800 Received: by xsj-xw9400.xilinx.com (Postfix, from userid 21952) id 29688600131; Fri, 4 Mar 2022 21:11:08 -0800 (PST) From: Lizhi Hou To: , , CC: Lizhi Hou , , , , , , , , , , Max Zhen Subject: [PATCH V1 2/4] Documentation: devicetree: bindings: add binding for PCIe endpoint bus Date: Fri, 4 Mar 2022 21:11:03 -0800 Message-ID: <20220305051105.725838-3-lizhi.hou@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220305051105.725838-1-lizhi.hou@xilinx.com> References: <20220305051105.725838-1-lizhi.hou@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9c53d7c5-7556-4260-caaa-08d9fe669665 X-MS-TrafficTypeDiagnostic: SJ0PR02MB8846:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou --- .../devicetree/bindings/bus/pci-ep-bus.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/pci-ep-bus.yaml diff --git a/Documentation/devicetree/bindings/bus/pci-ep-bus.yaml b/Documentation/devicetree/bindings/bus/pci-ep-bus.yaml new file mode 100644 index 000000000000..0ca96298db6f --- /dev/null +++ b/Documentation/devicetree/bindings/bus/pci-ep-bus.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/pci-ep-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe Endpoint Bus binding + +description: | + PCIe device may use flattened device tree to describe apertures in its + PCIe BARs. The Bus PCIe endpoint node is created and attached under the + device tree root node for this kind of device. Then the flatten device + tree overlay for this device is attached under the endpoint node. + + The aperture address which is under the endpoint node consists of BAR + index and offset. It uses the following encoding: + + 0xIooooooo 0xoooooooo + + Where: + + I = BAR index + oooooo oooooooo = BAR offset + + The endpoint is compatible with 'simple-bus' and contains 'ranges' + property for translating aperture address to CPU address. + +allOf: + - $ref: /schemas/simple-bus.yaml# + +maintainers: + - Lizhi Hou + +properties: + compatible: + contains: + const: pci-ep-bus + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +patternProperties: + "^.*@[0-9a-f]+$": + description: hardware apertures belong to this device. + type: object + +required: + - compatible + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + pci-ep-bus@e0000000 { + compatible = "pci-ep-bus", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xe0000000 0x0 0x2000000 + 0x20000000 0x0 0x0 0xe4200000 0x0 0x40000>; + }; + };