From patchwork Tue Mar 1 20:31:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 547326 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19321C433FE for ; Tue, 1 Mar 2022 20:32:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236126AbiCAUcs (ORCPT ); Tue, 1 Mar 2022 15:32:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237536AbiCAUcr (ORCPT ); Tue, 1 Mar 2022 15:32:47 -0500 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A9CF2DE8; Tue, 1 Mar 2022 12:32:02 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id C4D051F44A12 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1646166720; bh=rZ+zdH3XV8cnIuP17vc0Q44PQylfiOCJrNa2j1++0eE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gx6vs5RfgGPCHgc9F0RwhKN9G6d9f1L/S+6hQqi2cUaS0sRPPvWbkGAgHQalDbHMp zEoxSimyRWXawr28YTxKBy9+YlmaQlxzZQdP4a/8EXjxBcH2aRdEx1mJAgniiPNZ2L 1Zx1r0Qlr1LvwAvVYgOjmdFSngt9RWSGunfL0GRc5eYpV1eiRL2MHPJx0j5qR6gYnm euNOpoSMTYBDo9rQdnlM266y0RRV9BT33MNSilVRQY3SFgqEM4419F/NO+rPtcapLE NMiKW8t2IllrEGOZTvRB9WH7uV9y+THxgLDUrNvTCzoCwMfwIq7qH0WPG9xl6RU0Y6 SiZepdLlwfcLA== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: Rob Herring , AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 2/2] arm64: dts: mediatek: Format mediatek,larbs as an array of phandles Date: Tue, 1 Mar 2022 15:31:47 -0500 Message-Id: <20220301203147.1143782-2-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220301203147.1143782-1-nfraprado@collabora.com> References: <20220301203147.1143782-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Commit 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas") updated the mediatek,larbs property in the mediatek,iommu.yaml dt-binding to make it clearer that the phandles passed to the property are independent, rather than subsequent arguments to the first phandle. Update the mediatek,larbs property in the arm64 Devicetrees to use the same formatting. This change doesn't impact any behavior: the compiled dtb is exactly the same. It does however fix the warnings generated by dtbs_check. Signed-off-by: Nícolas F. R. A. Prado --- Changes in v2: - Split arm and arm64 changes into separate commits arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 6 +++--- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index de16c0d80c30..973c9beade0c 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -329,8 +329,8 @@ iommu0: iommu@10205000 { interrupts = ; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 - &larb3 &larb6>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb3>, <&larb6>; #iommu-cells = <1>; }; @@ -346,7 +346,7 @@ iommu1: iommu@1020a000 { interrupts = ; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; - mediatek,larbs = <&larb4 &larb5 &larb7>; + mediatek,larbs = <&larb4>, <&larb5>, <&larb7>; #iommu-cells = <1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 9029051624a6..54655f2feb04 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -174,7 +174,7 @@ larb2: larb@16010000 { iommu: m4u@10203000 { compatible = "mediatek,mt8167-m4u"; reg = <0 0x10203000 0 0x1000>; - mediatek,larbs = <&larb0 &larb1 &larb2>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>; interrupts = ; #iommu-cells = <1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 2b7d331a4588..042feaedda4a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -588,8 +588,8 @@ iommu: iommu@10205000 { interrupts = ; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 - &larb3 &larb4 &larb5>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb3>, <&larb4>, <&larb5>; #iommu-cells = <1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 00f2ddd245e1..523741150968 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -682,8 +682,8 @@ iommu: iommu@10205000 { compatible = "mediatek,mt8183-m4u"; reg = <0 0x10205000 0 0x1000>; interrupts = ; - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 - &larb4 &larb5 &larb6>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, + <&larb4>, <&larb5>, <&larb6>; #iommu-cells = <1>; };