From patchwork Sat Feb 26 18:41:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 546227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA35CC433F5 for ; Sat, 26 Feb 2022 18:42:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232413AbiBZSm5 (ORCPT ); Sat, 26 Feb 2022 13:42:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232808AbiBZSmn (ORCPT ); Sat, 26 Feb 2022 13:42:43 -0500 Received: from mail-qk1-x734.google.com (mail-qk1-x734.google.com [IPv6:2607:f8b0:4864:20::734]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2DE8E1E694C; Sat, 26 Feb 2022 10:42:04 -0800 (PST) Received: by mail-qk1-x734.google.com with SMTP id c7so7290711qka.7; Sat, 26 Feb 2022 10:42:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+yaSPMv2BtTagOAgtoROuKpbWEg+BWczZUb9gWsIWmQ=; b=BVjrRY4QdbPPVa/Ga31edyLqzJzVSRBZ28F7XLB7y6Gk6CATF0wxHqpRU3nVZ6NF7V LnMHKhwePZAMceonFeKhATrlVWuWUBZfjLSE7N20V7gWtt1zcO+mDe72LH3lwNEBbKQY N2/6U25mo+mc43OVUIUspNEzEkFsKcVADNpsQqLY8Nvzk6uaevaSkWsoaOwx5XrBa5J0 4SCff6KsPKaqq4Sv3wJ8sYmAF/vaT0LK2u+Bcvp0WA/9oIgxxjR8Fa/zFXKaUXdWRdw5 cStKDWRkIHOjYtCQ6Ro1hgub2FUfFOH9PoHmAvT/9abU16GflTVzezkNL7n3V0UVIjE4 4XtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+yaSPMv2BtTagOAgtoROuKpbWEg+BWczZUb9gWsIWmQ=; b=EcSSXh/IaTs/AeYLn3UdcAYTGOpnNRlWvsSflChYE8jqx/C2eS0sp8L2QkRbjUBXcK mTRHnmBbq0NArl4i1cga4J/yO3BmCFhhUa167nuECoVkovAq1gyqxIxFP9kYhUeBVyDp BKK6hq4L8fv0wHh3g2XTKRVWTCDmfboCs7nRP/RhKcKTFWSkntCe0ytDDmHxVzZIkgrE L7e2CNwVoYjEq7VOGEM3hPZ5BUCthxqhAyu4ly50q0JA0kXYGamwKX1JnyXBi0iuCpWM RRNz09miLATwwq/iQof9qSoLm5HV0LRMy77NSfbkbKZyzXWFbcFj47N+oB1gNpKalmGr DcMw== X-Gm-Message-State: AOAM531+uAWYbQBNQj60ae4D/G0E0+J1WeeH0SgoKQW5CSGLkqnep+tR jOX+MW2xpU2E8ueo/ocbWGI= X-Google-Smtp-Source: ABdhPJxewpoNGnB1rqTP28hOGbYOWjPjsdtQGZvo3lr/QpabuOPsc6HW6Lb+sChdKhTzKY5BV6xDow== X-Received: by 2002:a37:bb47:0:b0:506:993b:92f8 with SMTP id l68-20020a37bb47000000b00506993b92f8mr7843746qkf.57.1645900923275; Sat, 26 Feb 2022 10:42:03 -0800 (PST) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id p68-20020a378d47000000b006491d2d1450sm2891983qkd.10.2022.02.26.10.42.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Feb 2022 10:42:03 -0800 (PST) From: Peter Geis To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, michael.riesch@wolfvision.net, Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/11] arm64: dts: rockchip: add rk356x dwc3 usb3 nodes Date: Sat, 26 Feb 2022 13:41:45 -0500 Message-Id: <20220226184147.769964-10-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220226184147.769964-1-pgwipeout@gmail.com> References: <20220226184147.769964-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the dwc3 device nodes to the rk356x device trees. The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable dwc3 host controller. The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable dwc3 host controller. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk3566.dtsi | 12 +++++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 9 +++++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 45 +++++++++++++++++++++++- 3 files changed, 65 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi index 3839eef5e4f7..a57eb68faba2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi @@ -6,6 +6,10 @@ / { compatible = "rockchip,rk3566"; }; +&pipegrf { + compatible = "rockchip,rk3566-pipe-grf", "syscon"; +}; + &power { power-domain@RK3568_PD_PIPE { reg = ; @@ -18,3 +22,11 @@ power-domain@RK3568_PD_PIPE { #power-domain-cells = <0>; }; }; + +&usb_host0_xhci { + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 5b0f528d6818..8ba9334f9753 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -99,6 +99,10 @@ opp-1992000000 { }; }; +&pipegrf { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; +}; + &power { power-domain@RK3568_PD_PIPE { reg = ; @@ -114,3 +118,8 @@ power-domain@RK3568_PD_PIPE { #power-domain-cells = <0>; }; }; + +&usb_host0_xhci { + phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 7cdef800cb3c..b22e5a514ad7 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -230,6 +230,50 @@ scmi_shmem: sram@0 { }; }; + usb_host0_xhci: usb@fcc00000 { + compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfcc00000 0x0 0x400000>; + interrupts = ; + clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + dr_mode = "host"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG0>; + reset-names = "usb3-otg"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,xhci-trb-ent-quirk; + status = "disabled"; + }; + + usb_host1_xhci: usb@fd000000 { + compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfd000000 0x0 0x400000>; + interrupts = ; + clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + dr_mode = "host"; + phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG1>; + reset-names = "usb3-otg"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + gic: interrupt-controller@fd400000 { compatible = "arm,gic-v3"; reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ @@ -297,7 +341,6 @@ pmu_io_domains: io-domains { }; pipegrf: syscon@fdc50000 { - compatible = "rockchip,rk3568-pipe-grf", "syscon"; reg = <0x0 0xfdc50000 0x0 0x1000>; };