From patchwork Fri Feb 18 18:12:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 543847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 580B6C433F5 for ; Fri, 18 Feb 2022 18:12:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239032AbiBRSNE (ORCPT ); Fri, 18 Feb 2022 13:13:04 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239031AbiBRSND (ORCPT ); Fri, 18 Feb 2022 13:13:03 -0500 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D67535DFC; Fri, 18 Feb 2022 10:12:45 -0800 (PST) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id EBF6D2000A; Fri, 18 Feb 2022 18:12:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1645207964; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WeWTdPDyu4NpqtMlrcHJAByNbSFMRLqvNKamFBzDCiw=; b=hwrEYOrT3Q09uGn1ADsiKkh5rl59PBuo98xng1ZK2gQjJKtGQV1+cKK4PReH9k1dBG9AWI oQro+pnRxWSIjgAq9AnGFMWJLZ/TCPntTK7mO3JSYx2gHWrOCKhLdbHcWsJ7xXKcoft4Dc FtCZ2pJZ0flVYNIjqnnnc7JzQskq1o4Uo+pgXZEr+2XzKbDh/sMKEGQ8H43xUULojTxD8k 8hFjBAa/sENIBCm87/o19Q+A22YXGLU+fxRt8mrlRbsEPlWp2ddCY/D5Wyb4rjR6KJVx4L bnDh2yZxALfW6dCNrYv6opvxhjgiu4IFq0ZiIHT7P9IzySBwK4lwhpcG7JokBA== From: Miquel Raynal To: Viresh Kumar , Andy Shevchenko , Vinod Koul , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd Cc: Rob Herring , , dmaengine@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Milan Stevanovic , Jimmy Lalande , Laetitia MARIOTTINI , Miquel Raynal Subject: [PATCH 7/8] ARM: dts: r9a06g032: Add the two DMA nodes Date: Fri, 18 Feb 2022 19:12:25 +0100 Message-Id: <20220218181226.431098-8-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220218181226.431098-1-miquel.raynal@bootlin.com> References: <20220218181226.431098-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Describe the two DMA controllers available on this SoC. Signed-off-by: Miquel Raynal --- arch/arm/boot/dts/r9a06g032.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index db657224688a..640c3eb4bbcd 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -184,6 +184,36 @@ nand_controller: nand-controller@40102000 { status = "disabled"; }; + dma0: dma-controller@40104000 { + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; + reg = <0x40104000 0x1000>; + interrupts = ; + clock-names = "hclk"; + clocks = <&sysctrl R9A06G032_HCLK_DMA0>; + dma-channels = <8>; + dma-requests = <16>; + dma-masters = <1>; + #dma-cells = <3>; + block_size = <0xfff>; + data_width = <3>; + status = "disabled"; + }; + + dma1: dma-controller@40105000 { + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; + reg = <0x40105000 0x1000>; + interrupts = ; + clock-names = "hclk"; + clocks = <&sysctrl R9A06G032_HCLK_DMA1>; + dma-channels = <8>; + dma-requests = <16>; + dma-masters = <1>; + #dma-cells = <3>; + block_size = <0xfff>; + data_width = <3>; + status = "disabled"; + }; + gic: interrupt-controller@44101000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; interrupt-controller;