From patchwork Thu Feb 10 21:40:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 541549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8858EC433FE for ; Thu, 10 Feb 2022 21:40:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344743AbiBJVkq (ORCPT ); Thu, 10 Feb 2022 16:40:46 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344699AbiBJVkh (ORCPT ); Thu, 10 Feb 2022 16:40:37 -0500 Received: from mail-oi1-x22e.google.com (mail-oi1-x22e.google.com [IPv6:2607:f8b0:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89F5426C2 for ; Thu, 10 Feb 2022 13:40:37 -0800 (PST) Received: by mail-oi1-x22e.google.com with SMTP id x193so7554598oix.0 for ; Thu, 10 Feb 2022 13:40:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3nB7qzXaFNatnaTZQJRAInnjQf9KiqCTDZAFaYuusV0=; b=L+ZGFYNRoNLbHVhM3KhtWzMWcXEDYyJA7aw1jmcFUNm9LwjalIvnug5gAOBoaVsGAi XAfgYWak1dxQzZ5ghazPUUea8fGTUL4XYyIyS3b6NW+CmQgYLVmzlmTGPyvdu36ntJE9 p/WWwPx2fjkcKd0nUagR9y6sxwOG6zjfJTQ/wWjLi9u+NSP/xV0hSdCGSkoc8CSEy4Zh Xfmpchix/fMksPHav7pOiVse8m4TiWBP74rJVn9fBN60F/vQOUJa2ip5dMXv/LouxZAc odHYF6dZ+iuK1KlWP32f8JPsVtkzl9VjkswCDQuIxLTMaPXm3Tnh3rK4m5SBJ5wSZl2Y E93g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3nB7qzXaFNatnaTZQJRAInnjQf9KiqCTDZAFaYuusV0=; b=FZVSjH0f4VmoyakyT3Of8/QEPZfqp+oomfnmQ+hLZOx2v0+59K3wmSYtnAgGeyNZeG GGPnsaOtzWCvmT3naJLmO+MWPAKNjK0nwfWUWn75cXcsWEvP/rE8oyLp58eEhr3M3NCh 7bjyKtoXCrpOTB3XF7ewYxUc5oHVlObogQoULo5o82p4QHXaqhPTaKgur3AX/etEi/YX Q85S6wwrFQBD3Fv2T6KfVuW+BvcwO9+BM4SDee2199DG9mf/qmKZMgyhNbG2pHg3gIv0 UtquUVMDEyJKbtzBbk2XCTK9Gl3RrQ6uh2L/lAiiUbVMbpBUT3g0aWahvq9a8n2Po+P2 c7Cg== X-Gm-Message-State: AOAM530n6WvLRR3R2njcwngbFgZhszorlJ6Edt7fh3QF/x77z3g3zw0Q YalaVL2CnVEXnQaK+LkRZI3Ceg== X-Google-Smtp-Source: ABdhPJxnj59RepTjd/uznzgrpDdO30O9r7af3cgqYy9BVCSUocaHEleDWBfL7GJ76jB38zMSSwzmAQ== X-Received: by 2002:a05:6808:11ca:: with SMTP id p10mr1942733oiv.74.1644529236740; Thu, 10 Feb 2022 13:40:36 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id u5sm8700000ooo.46.2022.02.10.13.40.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Feb 2022 13:40:36 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v2 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Date: Thu, 10 Feb 2022 13:40:17 -0800 Message-Id: <20220210214018.55739-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220210214018.55739-1-atishp@rivosinc.com> References: <20220210214018.55739-1-atishp@rivosinc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The isa string should begin with either rv64 or rv32. Otherwise, it is an incorrect isa string. Currently, the string parsing continues even if it doesnot begin with current XLEN. Fix this by checking if it found "rv64" or "rv32" in the beginning. Signed-off-by: Atish Patra --- arch/riscv/kernel/cpufeature.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 469b9739faf7..cca579bae8a0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void) for_each_of_cpu_node(node) { unsigned long this_hwcap = 0; uint64_t this_isa = 0; + char *temp; if (riscv_of_processor_hartid(node) < 0) continue; @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void) continue; } + temp = (char *)isa; #if IS_ENABLED(CONFIG_32BIT) if (!strncmp(isa, "rv32", 4)) isa += 4; @@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void) if (!strncmp(isa, "rv64", 4)) isa += 4; #endif + /* The riscv,isa DT property must start with rv64 or rv32 */ + if (temp == isa) + continue; for (; *isa; ++isa) { const char *ext = isa++; const char *ext_end = isa;