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[98.233.193.225]) by smtp.gmail.com with ESMTPSA id t1sm2142883qtc.48.2022.01.27.16.38.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 16:38:17 -0800 (PST) From: Peter Geis To: Rob Herring , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/4] arm64: dts: rockchip: add Quartz64-A sdmmc1 node Date: Thu, 27 Jan 2022 19:38:07 -0500 Message-Id: <20220128003809.3291407-4-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128003809.3291407-1-pgwipeout@gmail.com> References: <20220128003809.3291407-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The sdmmc1 node on Quartz64-A supports the optional wifi module from Pine64. Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on the Quartz64-A. Signed-off-by: Peter Geis --- Changelog: v2: - drop status = "okay" from sdio_pwrseq - drop disable-wp from sdmmc1 - move reset-gpios to be alphabetical in sdio_pwrseq --- .../boot/dts/rockchip/rk3566-quartz64-a.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 33c2c18caaa9..c5a79046a9d0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -91,6 +91,17 @@ simple-audio-card,codec { }; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + }; + vcc12v_dcin: vcc12v_dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -147,6 +158,17 @@ vcc_sys: vcc_sys { regulator-max-microvolt = <4400000>; vin-supply = <&vbus>; }; + + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ + vcc_wl: vcc_wl { + compatible = "regulator-fixed"; + regulator-name = "vcc_wl"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; }; &cpu0 { @@ -475,6 +497,12 @@ pmic_int_l: pmic-int-l { }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vcc_sd { vcc_sd_h: vcc-sd-h { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; @@ -516,6 +544,21 @@ &sdmmc0 { status = "okay"; }; +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_wl>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + &spdif { status = "okay"; };