diff mbox series

[net-next,v2,1/3] dt-bindings: net: cdns,macb: added generic PHY and reset mappings for ZynqMP

Message ID 20220125170533.256468-2-robert.hancock@calian.com
State New
Headers show
Series Cadence MACB/GEM support for ZynqMP SGMII | expand

Commit Message

Robert Hancock Jan. 25, 2022, 5:05 p.m. UTC
Updated macb DT binding documentation to reflect the phy-names, phys,
resets, reset-names properties which are now used with ZynqMP GEM
devices, and added a ZynqMP-specific DT example.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
 .../devicetree/bindings/net/cdns,macb.yaml    | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)

Comments

Rob Herring (Arm) Jan. 26, 2022, 3:29 a.m. UTC | #1
On Tue, 25 Jan 2022 11:05:31 -0600, Robert Hancock wrote:
> Updated macb DT binding documentation to reflect the phy-names, phys,
> resets, reset-names properties which are now used with ZynqMP GEM
> devices, and added a ZynqMP-specific DT example.
> 
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>
> ---
>  .../devicetree/bindings/net/cdns,macb.yaml    | 46 +++++++++++++++++++
>  1 file changed, 46 insertions(+)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/net/cdns,macb.example.dts:41.39-40 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:378: Documentation/devicetree/bindings/net/cdns,macb.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1398: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1584186

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml
index 8dd06db34169..efc759e052c4 100644
--- a/Documentation/devicetree/bindings/net/cdns,macb.yaml
+++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml
@@ -81,6 +81,25 @@  properties:
 
   phy-handle: true
 
+  phys:
+    maxItems: 1
+
+  phy-names:
+    const: sgmii-phy
+    description:
+      Required with ZynqMP SoC when in SGMII mode.
+      Should reference PS-GTR generic PHY device for this controller
+      instance. See ZynqMP example.
+
+  resets:
+    maxItems: 1
+    description:
+      Recommended with ZynqMP, specify reset control for this
+      controller instance with zynqmp-reset driver.
+
+  reset-names:
+    maxItems: 1
+
   fixed-link: true
 
   iommus:
@@ -157,3 +176,30 @@  examples:
                     reset-gpios = <&pioE 6 1>;
             };
     };
+
+    gem1: ethernet@ff0c0000 {
+            compatible = "cdns,zynqmp-gem", "cdns,gem";
+            interrupt-parent = <&gic>;
+            interrupts = <0 59 4>, <0 59 4>;
+            reg = <0x0 0xff0c0000 0x0 0x1000>;
+            clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
+                     <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
+                     <&zynqmp_clk GEM_TSU>;
+            clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+            #address-cells = <1>;
+            #size-cells = <0>;
+            #stream-id-cells = <1>;
+            iommus = <&smmu 0x875>;
+            power-domains = <&zynqmp_firmware PD_ETH_1>;
+            resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
+            reset-names = "gem1_rst";
+            status = "okay";
+            phy-mode = "sgmii";
+            phy-names = "sgmii-phy";
+            phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>;
+            fixed-link {
+                    speed = <1000>;
+                    full-duplex;
+                    pause;
+            };
+    };