From patchwork Fri Jan 7 23:53:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 530553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96CAAC433F5 for ; Fri, 7 Jan 2022 23:53:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231979AbiAGXxp (ORCPT ); Fri, 7 Jan 2022 18:53:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231909AbiAGXxl (ORCPT ); Fri, 7 Jan 2022 18:53:41 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29DDAC061747 for ; Fri, 7 Jan 2022 15:53:38 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id n30-20020a17090a5aa100b001b2b6509685so8232770pji.3 for ; Fri, 07 Jan 2022 15:53:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uqA2vTRTwCd5lb+1bpw59I8A4YOj+PxA4CFZWdTkSiE=; b=KjQjjOwC8d4WeVLXIzAl5ZiDLmf1td57rlGuw1GCTyOix4NbWz87jaIU3GPeaHkhs2 +aKtbG6eMTbXncBI8DqE362s9f/7hyyLlEFnDyCIssQVbVjfuNX3Ig4LPvwuuJx9CHy3 4H3ahd/fdtvy4tK0RwPpQ0oebhP89pSmGlBC0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uqA2vTRTwCd5lb+1bpw59I8A4YOj+PxA4CFZWdTkSiE=; b=TbDLPGkBIxuoJu60QAVGNSCtf12x+tdDEjkTJJOw3mNoGzoc7unZyJLhg/AP5z1suf ivzdgcPmj72cxFiEGTs8SJvE1lMXGVJnHCpba9C7iXhCsX0hHY08oDSVUToXojfw4nKT x2G2GGjNVcKDzzEF0j8taunMJCAIW0wRK9YNaA0F5tlhIHW8QyX3V5/QRUxI3zwO/c8m WXHmmOPxuAUnXytsFUzVnsNndvCsPLSY9hndQZ7PLew/kT7BRya5xG9N+IP7E0fdCDCp kdq6MWPH7x8hxpDAlsoxJEHGmYrBf5NNMq+PExAX5UADhqwqCILe/uGEKlcN0iHH5B4n UhiQ== X-Gm-Message-State: AOAM531FAWsjryrfb0fODUBdCP5UZ8OToSDD3rRecy1LKeTcGWhb9D75 4iwol+YcS9LP+KPZ7Z/jJd+z5Q== X-Google-Smtp-Source: ABdhPJwIGLUJ4870oxOMvvNEBPUvoGuIBVIO34djfW+MF+nHRtQ6skGcluLNSZvfeaLmcwPvyDn+Tw== X-Received: by 2002:a17:90a:df04:: with SMTP id gp4mr2131418pjb.148.1641599617740; Fri, 07 Jan 2022 15:53:37 -0800 (PST) Received: from localhost ([2620:15c:202:201:db:1c60:693f:c24e]) by smtp.gmail.com with UTF8SMTPSA id h19sm57446pfh.30.2022.01.07.15.53.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Jan 2022 15:53:37 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Lin Huang , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, Derek Basehore , linux-kernel@vger.kernel.org, Brian Norris Subject: [PATCH 04/10] dt-bindings: devfreq: rk3399_dmc: Add more disable-freq properties Date: Fri, 7 Jan 2022 15:53:14 -0800 Message-Id: <20220107155215.4.I382d4de737198ea52deb118c9bdc4d93d76e009e@changeid> X-Mailer: git-send-email 2.34.1.575.g55b058a8bb-goog In-Reply-To: <20220107235320.965497-1-briannorris@chromium.org> References: <20220107235320.965497-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org DDR DVFS tuning has found that several power-saving features don't have good tradeoffs at higher frequencies -- at higher frequencies, we'll see glitches or other errors. Provide tuning controls so these can be disabled at higher OPPs, and left active only at the lower ones. Signed-off-by: Brian Norris --- .../bindings/devfreq/rk3399_dmc.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml index 2c871c57fd97..357d07c5a3df 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml @@ -271,6 +271,43 @@ properties: When the DRAM type is LPDDR4, this parameter defines the PHY side ODT strength. Default value is 60. + rockchip,pd_idle_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the power-down idle disable frequency in Hz. When the DDR + frequency is greater than pd_idle_dis_freq, power-down idle is disabled. + See also rockchip,pd_idle. + + rockchip,sr_idle_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the self-refresh idle disable frequency in Hz. When the DDR + frequency is greater than sr_idle_dis_freq, self-refresh idle is + disabled. See also rockchip,sr_idle. + + rockchip,sr_mc_gate_idle_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the self-refresh and memory-controller clock gating disable + frequency in Hz. When the DDR frequency is greater than + sr_mc_gate_idle_dis_freq, the clock will not be gated when idle. See also + rockchip,sr_mc_gate_idle. + + rockchip,srpd_lite_idle_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the self-refresh power down idle disable frequency in Hz. When + the DDR frequency is greater than srpd_lite_idle_dis_freq, memory will + not be placed into self-refresh power down mode when idle. See also + rockchip,srpd_lite_idle. + + rockchip,standby_idle_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the standby idle disable frequency in Hz. When the DDR frequency + is greater than standby_idle_dis_freq, standby idle is disabled. See also + rockchip,standby_idle. + additionalProperties: false examples: @@ -294,4 +331,9 @@ examples: rockchip,ddr3_odt_dis_freq = <333000000>; rockchip,lpddr3_odt_dis_freq = <333000000>; rockchip,lpddr4_odt_dis_freq = <333000000>; + rockchip,pd_idle_dis_freq = <1000000000>; + rockchip,sr_idle_dis_freq = <1000000000>; + rockchip,sr_mc_gate_idle_dis_freq = <1000000000>; + rockchip,srpd_lite_idle_dis_freq = <0>; + rockchip,standby_idle_dis_freq = <928000000>; };