From patchwork Thu Dec 30 08:48:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yifeng Zhao X-Patchwork-Id: 529023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4E9CC4332F for ; Thu, 30 Dec 2021 08:48:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237942AbhL3Isi (ORCPT ); Thu, 30 Dec 2021 03:48:38 -0500 Received: from lucky1.263xmail.com ([211.157.147.135]:51608 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234712AbhL3Ish (ORCPT ); Thu, 30 Dec 2021 03:48:37 -0500 Received: from localhost (unknown [192.168.167.16]) by lucky1.263xmail.com (Postfix) with ESMTP id CDBC3B6769; Thu, 30 Dec 2021 16:48:29 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-SKE-CHECKED: 1 X-ANTISPAM-LEVEL: 2 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P12624T140277015766784S1640854098676227_; Thu, 30 Dec 2021 16:48:30 +0800 (CST) X-IP-DOMAINF: 1 X-RL-SENDER: yifeng.zhao@rock-chips.com X-SENDER: zyf@rock-chips.com X-LOGIN-NAME: yifeng.zhao@rock-chips.com X-FST-TO: heiko@sntech.de X-RCPT-COUNT: 17 X-LOCAL-RCPT-COUNT: 4 X-MUTI-DOMAIN-COUNT: 0 X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-UNIQUE-TAG: X-System-Flag: 0 From: Yifeng Zhao To: heiko@sntech.de Cc: robh+dt@kernel.org, jbx6244@gmail.com, devicetree@vger.kernel.org, vkoul@kernel.org, michael.riesch@wolfvision.net, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, kishon@ti.com, p.zabel@pengutronix.de, cl@rock-chips.com, kever.yang@rock-chips.com, lee.jones@linaro.org, wulf@rock-chips.com, Yifeng Zhao Subject: [PATCH v7 1/4] dt-bindings: mfd: syscon: add naneng combo phy register compatible Date: Thu, 30 Dec 2021 16:48:12 +0800 Message-Id: <20211230084815.28110-2-yifeng.zhao@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211230084815.28110-1-yifeng.zhao@rock-chips.com> References: <20211230084815.28110-1-yifeng.zhao@rock-chips.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Johan Jonker Add naneng combo phy register compatible. Acked-by: Rob Herring Signed-off-by: Johan Jonker Signed-off-by: Yifeng Zhao --- Changes in v7: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index fdd96e378df0..e9bb96ab9446 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -52,6 +52,8 @@ properties: - rockchip,rk3288-qos - rockchip,rk3368-qos - rockchip,rk3399-qos + - rockchip,rk3568-pipe-grf + - rockchip,rk3568-pipe-phy-grf - rockchip,rk3568-qos - samsung,exynos3-sysreg - samsung,exynos4-sysreg