From patchwork Thu Dec 23 19:16:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 527507 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92FDFC433EF for ; Thu, 23 Dec 2021 19:16:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349975AbhLWTQu (ORCPT ); Thu, 23 Dec 2021 14:16:50 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:47578 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349965AbhLWTQu (ORCPT ); Thu, 23 Dec 2021 14:16:50 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1BNJGjL9029367; Thu, 23 Dec 2021 13:16:45 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1640287005; bh=hugen2iF9pOeMe2j/Up7HEzH64lhEKNpA6zbe/IDWdY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cX4J+0PjZsvPnFONO2i7b4MWXWd6qkloDWMKEm9FPXs3u9i3eUTC4qKY1oMcVuUZ6 70HXpVrg0arUWRxt0y8Ut+zyaH7ww3A152z2j+n63v5QbIBK4kbiXyPu8Zzl2KsYsu vtKIws/1eD/dTihuv0ft6rNxl9g8yyocZuZPd5YA= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1BNJGjBf006692 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 23 Dec 2021 13:16:45 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Thu, 23 Dec 2021 13:16:44 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 23 Dec 2021 13:16:44 -0600 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1BNJGGQT006164; Thu, 23 Dec 2021 13:16:41 -0600 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Vignesh Raghavendra , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlun?= =?utf-8?q?d?= , , , Subject: [PATCH v5 06/14] media: cadence: csi2rx: Set the STOP bit when stopping a stream Date: Fri, 24 Dec 2021 00:46:07 +0530 Message-ID: <20211223191615.17803-7-p.yadav@ti.com> X-Mailer: git-send-email 2.33.1.835.ge9e5ba39a7 In-Reply-To: <20211223191615.17803-1-p.yadav@ti.com> References: <20211223191615.17803-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The stream stop procedure says that the STOP bit should be set when the stream is to be stopped, and then the ready bit in stream status register polled to make sure the STOP operation is finished. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart --- Changes in v5: - Change %d to %u - Add Laurent's R-by. drivers/media/platform/cadence/cdns-csi2rx.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index baf8ec649a25..86546074c555 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -40,8 +41,12 @@ #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) #define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) +#define CSI2RX_STREAM_CTRL_STOP BIT(1) #define CSI2RX_STREAM_CTRL_START BIT(0) +#define CSI2RX_STREAM_STATUS_REG(n) (CSI2RX_STREAM_BASE(n) + 0x004) +#define CSI2RX_STREAM_STATUS_RDY BIT(31) + #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) #define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT BIT(31) #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16) @@ -312,12 +317,23 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) static void csi2rx_stop(struct csi2rx_priv *csi2rx) { unsigned int i; + u32 val; + int ret; clk_prepare_enable(csi2rx->p_clk); clk_disable_unprepare(csi2rx->sys_clk); for (i = 0; i < csi2rx->max_streams; i++) { - writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + writel(CSI2RX_STREAM_CTRL_STOP, + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + + ret = readl_relaxed_poll_timeout(csi2rx->base + + CSI2RX_STREAM_STATUS_REG(i), + val, + (val & CSI2RX_STREAM_STATUS_RDY), + 10, 10000); + if (ret) + dev_warn(csi2rx->dev, "Failed to stop stream%u\n", i); clk_disable_unprepare(csi2rx->pixel_clk[i]); }