From patchwork Sat Dec 11 02:17:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 523173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D8CCC35264 for ; Sat, 11 Dec 2021 02:18:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238399AbhLKCVt (ORCPT ); Fri, 10 Dec 2021 21:21:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240167AbhLKCVr (ORCPT ); Fri, 10 Dec 2021 21:21:47 -0500 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81FA3C0617A2 for ; Fri, 10 Dec 2021 18:18:11 -0800 (PST) Received: by mail-lf1-x12d.google.com with SMTP id bi37so21205889lfb.5 for ; Fri, 10 Dec 2021 18:18:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6ZUxtcLKEJ/zzIBic4E9biaq2SmRM4VjIAbxiOeDh58=; b=RLEnCp81okcB655NrV6bJm4T2Dqn+jFGYT9TU2miDEegKYh2RmjTt//VKjE/7bkNzF RNycO/RF/F36L48mkujsqQ+vbRLlwQMbipAmC9QVHQx2UjphkB0Aylkc5phhbcGTbK/v 7yBpCuP7DusMRS9C35oyw2J7pBilqfmk/8mBgn/G7pMX+sHuAXl11e+pGnc3uBJpLEKE 0jAMOsNKI8OD8FKaBhgZXoj83WAaGdKXZFlCUPQ/vjaYtvdXY8yG25/ePz6ifsrK9d28 MuFF6++y29eRHObpsJon8mYqkeZmSkkElWUlESR1ijWeiAWrlvRelCUQmjvjWcxbHEJ4 QQjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6ZUxtcLKEJ/zzIBic4E9biaq2SmRM4VjIAbxiOeDh58=; b=ZxNUF+hRP6djARaokrPpc7mcydEQPto6SxIxK51OAbclPjXfz85xNhFEWokdE8jhiL RbwVBdd242Q3be2heGU1dA2rveoQ4JU/FCUPqKPknKs3eGcGfuu59jIGtL/9M/daB5MB TZRtCNvcVkhfsDMzwRPh+QQVNT97Gcfsz9/uYnWiJOfMSjbRajJ+woiGiiU4HRL0ezJM StuCaXwb9zxRu5usZj1pgxzrnfaYgI+33H6eqjh89gTWoI+ZwAyZrBjGVBek+KqS26Ks e/SQnlmhu33FVe+tu6wVxbq9JW8EgltU4IHYSzFAEe/vtuHaZaMpZeqkzWdmqhlE9MTV sCqQ== X-Gm-Message-State: AOAM532DnAAJA4ZJhxllX+/wv/OSjvDIIejJIwCRK8VirGy+0XgBMi44 PK0rAIJacAk/HFzS7jMJ275PNA== X-Google-Smtp-Source: ABdhPJxNVUnTyGUA8g365qC2pbZ05wZIxDSRngWLY/TMk29Fxgaq2SrD9PTykKKGqElfjQ9J4LXwIA== X-Received: by 2002:ac2:54bc:: with SMTP id w28mr10604715lfk.405.1639189089777; Fri, 10 Dec 2021 18:18:09 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y7sm504663lfj.90.2021.12.10.18.18.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Dec 2021 18:18:08 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, Manivannan Sadhasivam Subject: [PATCH v3 08/10] arm64: dts: qcom: sm8450: add PCIe0 RC device Date: Sat, 11 Dec 2021 05:17:56 +0300 Message-Id: <20211211021758.1712299-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211211021758.1712299-1-dmitry.baryshkov@linaro.org> References: <20211211021758.1712299-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree node for the first PCIe host found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov Acked-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 101 +++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index a047d8a22897..09087a34a007 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -627,6 +627,84 @@ i2c14: i2c@a98000 { #size-cells = <0>; status = "disabled"; }; + ]; + + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sm8450"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_lane>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + iommus = <&apps_smmu 0x1c00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + power-domain-names = "gdsc"; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + perst-gpio = <&tlmm 94 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + interconnect-names = "pci"; + + status = "disabled"; }; pcie0_phy: phy@1c06000 { @@ -763,6 +841,29 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + pcie0_default_state: pcie0-default { + perst { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio95"; + function = "pcie0_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_i2c13_default_state: qup-i2c13-default-state { mux { pins = "gpio48", "gpio49";