From patchwork Fri Dec 3 16:54:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 520323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA523C433F5 for ; Fri, 3 Dec 2021 16:55:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382228AbhLCQ6a (ORCPT ); Fri, 3 Dec 2021 11:58:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240527AbhLCQ63 (ORCPT ); Fri, 3 Dec 2021 11:58:29 -0500 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDC20C061751 for ; Fri, 3 Dec 2021 08:55:05 -0800 (PST) Received: by mail-pl1-x635.google.com with SMTP id z6so2523813plk.6 for ; Fri, 03 Dec 2021 08:55:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TpS2YL61YHWZgUBV1xYwkCUo8ZrXNrqKv+qQZlMOcKU=; b=fkDmK2/7QbfpGUSzfAnG2GWFoqlztEHg8GsIediZsGV+iSsX9rPmbIenCsx9EMqIQo VzwnXh2IIcGOD9wBCGR4N3Pr8F2bQMXkq5HZTZiyDmbKi2qaHfWMnmOLZENGMK0AksoO 5ps12JZ5kobkB/JwouxZDNcbVDtX07esXedeg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TpS2YL61YHWZgUBV1xYwkCUo8ZrXNrqKv+qQZlMOcKU=; b=LlZM1BrNNfIT/ey6tUpayavzhVdx0IBxWdmmijyb+TFMQOOBt2Q+fMsOU3YjclvmRK 75fpUTW4xnD/geBBn9CNRg9hj+5Hc4ASzg8TVUXorZ00WCr2SNdwcG3DPmgdlSUyhqcD SeBrnID/oOmg6/CDlGE/Ek3IU0cHmDXQpJimzJ1zdEfEetVw/arUp3+oEd6bnUrNwUpF fyx4qVNP8IK1BztZyLh3zl1VYqYJJOAdKsdDzeYi8D/KP3qXwQ6EjzCdDF8xR8yd88S7 V1AC7LbY1TzJfYceIlrHrmw+XOaEW2PKw6KqGvfqsFkBazJ3/oDDhhtVOlcRW5bwLVmg ea/w== X-Gm-Message-State: AOAM533gjKzIcC+rG2fYEjtuJIsTjlxnoCIzXGW9GeIn1fRSGst/U9ti C7VNEDGr4sooQYKPyPxxvDi6aQ== X-Google-Smtp-Source: ABdhPJwgc3geQjKTnKBjpmGWy9Mp7ji+pJOvmJEealvqKz5JoNEk0k64bKXw+qIIfRZpsYN/jX+7cw== X-Received: by 2002:a17:90b:4b04:: with SMTP id lx4mr15463297pjb.11.1638550505453; Fri, 03 Dec 2021 08:55:05 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a0a9:9d21:588c:4f26:8400]) by smtp.gmail.com with ESMTPSA id s72sm2783693pgc.69.2021.12.03.08.54.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Dec 2021 08:55:05 -0800 (PST) From: Jagan Teki To: Rob Herring , Maxime Coquelin , Alexandre Torgue Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-amarula@amarulasolutions.com, Matteo Lisi , Jagan Teki Subject: [PATCH v3 3/3] ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF Date: Fri, 3 Dec 2021 22:24:35 +0530 Message-Id: <20211203165435.8042-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211203165435.8042-1-jagan@amarulasolutions.com> References: <20211203165435.8042-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - 10" LVDS Panel (SN65DSI84 DSI-LVDS bridge on SoM) i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0 10.1" Open Frame board. Add support for it. Signed-off-by: Jagan Teki --- Changes for v3: - drop redundent commit details. - fix dtbs_check Changes for v2: - none arch/arm/boot/dts/Makefile | 1 + ...tm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 132 ++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8a2dfdf01ce3..47878c1e878b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1140,6 +1140,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ stm32mp157a-icore-stm32mp1-ctouch2.dtb \ + stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \ stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts new file mode 100644 index 000000000000..2a2829283456 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-icore-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include + +/ { + model = "Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1\" Open Frame"; + compatible = "engicam,icore-stm32mp1-ctouch2-of10", + "engicam,icore-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; + default-on; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + panel { + compatible = "ampire,am-1280800n3tzqw-t00h"; + backlight = <&backlight>; + power-supply = <&v3v3>; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; +}; + +&dsi { + status = "okay"; + phy-dsi-supply = <®18>; + + ports { + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + +&i2c6 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_pins_a>; + pinctrl-1 = <&i2c6_sleep_pins_a>; + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + data-lanes = <1 2>; + }; + }; + + port@2 { + reg = <2>; + bridge_out: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +};