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[23.128.96.18]) by mx.google.com with ESMTP id h7si1158223pgq.411.2021.10.07.18.25.57; Thu, 07 Oct 2021 18:25:58 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MAjGzOTW; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236675AbhJHB1q (ORCPT + 7 others); Thu, 7 Oct 2021 21:27:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230503AbhJHB1n (ORCPT ); Thu, 7 Oct 2021 21:27:43 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48294C0613E9 for ; Thu, 7 Oct 2021 18:25:42 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id x27so32285714lfa.9 for ; Thu, 07 Oct 2021 18:25:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1ZjqNWJNbpqp+wYhpfPdT4qYlEU1ULLxGhv3FpneW9Y=; b=MAjGzOTWzwVqMXeWy9koSr+ZsvOJydeBaNej7TfaJQ1IipAlHGpmUfBUf4i5PdwHx7 KVdxrTouGB+L8D9aiRcpDk9F3a9MaNyvOO5Uryn9vWNXRua3y4GS3puLmpe4+NJUFM8B YyvRbuhFnTtzd5WIMAX/5hHlnc3CWPW/D/3tmDlb/UJBtKoKWg5zcPlZGekcA5S5kbGL AScuarz5ZALDY6pvdkmaXWBwo2zAe1JFOddgZ4xqqdgttzhOy/S+oFlvtIUG/4bwrWAa NhEDM5bczmzlKMuXGQLfNT/zKqTf2qt9S356jU5uWj4J5L63g7fF5HG+Jv+uZ0lxqOZH GBjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1ZjqNWJNbpqp+wYhpfPdT4qYlEU1ULLxGhv3FpneW9Y=; b=kbDUVb4LhrUNEuQj77OuWjuNf13pji5r0Hv2veRrI6lKEFpmscpf1opZHYq73QirFC vXXWmuSPuzHu9Lj33qqFM6tnXHalti9PIs50XHFLiCGhpNnr34pabda1kcmp5J1jarPO QjcQuVKbQX5i2uF19UYWJgP+0IWGY+Q8hQEPuoP+RgO+D5IeEJo1ws/lIDdIErjzS60z fGLoC8tlYdUS5n63k8Rlh/W6kU20OjnBr7urha2KtTKrvcU2+yeUhxgbxRVEMYPFE1qV TCBVAE5IEJFqE7wJdzZNhBeQN+MMoQL2C9UfZG5JXNMH5YQOQLquekL2x/O0pzW4Y75o vYyg== X-Gm-Message-State: AOAM533y3HwwrdaXoYndE5A1lgZcktXShTGl8ksrBcfqocS9oUAlBPks qJM5y7nGU3PVSQO95KG+st+UAg== X-Received: by 2002:a2e:801a:: with SMTP id j26mr355117ljg.175.1633656340592; Thu, 07 Oct 2021 18:25:40 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:40 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 19/25] ARM: dts: qcom-mdm9615: add interrupt controller properties Date: Fri, 8 Oct 2021 04:25:18 +0300 Message-Id: <20211008012524.481877-20-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now that the pmic-mpp is a proper hierarchical IRQ chip, add interrupt controller properties ('interrupt-controller' and '#interrupt-cells'). The interrupts property is no longer needed so remove it. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) -- 2.30.2 diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index cfff1a5706ed..6e90c5d5a050 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -302,13 +302,8 @@ pwrkey@1c { pmicmpp: mpps@50 { compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; - interrupt-parent = <&pmicintc>; - interrupts = <24 IRQ_TYPE_NONE>, - <25 IRQ_TYPE_NONE>, - <26 IRQ_TYPE_NONE>, - <27 IRQ_TYPE_NONE>, - <28 IRQ_TYPE_NONE>, - <29 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x50>; gpio-controller; #gpio-cells = <2>;