From patchwork Tue Sep 14 02:16:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chun-Jie Chen X-Patchwork-Id: 512517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 011B5C433F5 for ; Tue, 14 Sep 2021 02:17:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DE58C60F12 for ; Tue, 14 Sep 2021 02:17:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237707AbhINCSU (ORCPT ); Mon, 13 Sep 2021 22:18:20 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:50624 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237186AbhINCSO (ORCPT ); Mon, 13 Sep 2021 22:18:14 -0400 X-UUID: 7726db85bf30494fa665be1482cf7a4c-20210914 X-UUID: 7726db85bf30494fa665be1482cf7a4c-20210914 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1583810653; Tue, 14 Sep 2021 10:16:55 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 14 Sep 2021 10:16:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 14 Sep 2021 10:16:53 +0800 From: Chun-Jie Chen To: Matthias Brugger , Stephen Boyd , Nicolas Boichat , Rob Herring CC: , , , , , , , Chun-Jie Chen Subject: [v3 03/24] clk: mediatek: Fix corner case of tuner_en_reg Date: Tue, 14 Sep 2021 10:16:12 +0800 Message-ID: <20210914021633.26377-4-chun-jie.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210914021633.26377-1-chun-jie.chen@mediatek.com> References: <20210914021633.26377-1-chun-jie.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On MT8195, tuner_en_reg is moved to register offest 0x0. If we only judge by tuner_en_reg, it may lead to wrong address. Add tuner_en_bit to the check condition. And it has been confirmed, on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by clock square control. Signed-off-by: Chun-Jie Chen Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 7fb001a4e7d8..99ada6e06697 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -332,7 +332,7 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, pll->pcw_chg_addr = pll->base_addr + REG_CON1; if (data->tuner_reg) pll->tuner_addr = base + data->tuner_reg; - if (data->tuner_en_reg) + if (data->tuner_en_reg || data->tuner_en_bit) pll->tuner_en_addr = base + data->tuner_en_reg; if (data->en_reg) pll->en_addr = base + data->en_reg;