From patchwork Fri Sep 10 20:26:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 508846 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A175BC433EF for ; Fri, 10 Sep 2021 20:26:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8989560E0B for ; Fri, 10 Sep 2021 20:26:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233808AbhIJU2E (ORCPT ); Fri, 10 Sep 2021 16:28:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233784AbhIJU2E (ORCPT ); Fri, 10 Sep 2021 16:28:04 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0764CC061574 for ; Fri, 10 Sep 2021 13:26:53 -0700 (PDT) Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mOn6k-0000xM-Rh; Fri, 10 Sep 2021 22:26:46 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v4 05/18] soc: imx: gpcv2: add domain option to keep domain clocks enabled Date: Fri, 10 Sep 2021 22:26:27 +0200 Message-Id: <20210910202640.980366-6-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210910202640.980366-1-l.stach@pengutronix.de> References: <20210910202640.980366-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some of the MIX domains are using clocks to drive the bus bridges. Those must be enabled at all times, as long as the domain is powered up and they don't have any other consumer than the power domain. Add an option to keep the clocks attached to a domain enabled as long as the domain is power up and only disable them after the domain is powered down. Signed-off-by: Lucas Stach Reviewed-by: Peng Fan --- drivers/soc/imx/gpcv2.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 35f26f57d1ac..c3b1d2580963 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -202,6 +202,7 @@ struct imx_pgc_domain { } bits; const int voltage; + const bool keep_clocks; struct device *dev; }; @@ -295,7 +296,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) } /* Disable reset clocks for all devices in the domain */ - clk_bulk_disable_unprepare(domain->num_clks, domain->clks); + if (!domain->keep_clocks) + clk_bulk_disable_unprepare(domain->num_clks, domain->clks); return 0; @@ -317,10 +319,12 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) int ret; /* Enable reset clocks for all devices in the domain */ - ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); - if (ret) { - dev_err(domain->dev, "failed to enable reset clocks\n"); - return ret; + if (!domain->keep_clocks) { + ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); + if (ret) { + dev_err(domain->dev, "failed to enable reset clocks\n"); + return ret; + } } /* request the ADB400 to power down */