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Thu, 19 Aug 2021 08:45:15 -0700 (PDT) Received: from localhost.localdomain ([86.32.42.198]) by smtp.gmail.com with ESMTPSA id f16sm1925373edw.79.2021.08.19.08.45.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Aug 2021 08:45:15 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Paul Walmsley , Palmer Dabbelt , Albert Ou , Krzysztof Kozlowski , Geert Uytterhoeven , Atish Patra , Yash Shah , Masahiro Yamada , Piotr Sroka , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 1/6] dt-bindings: riscv: correct e51 and u54-mc CPU bindings Date: Thu, 19 Aug 2021 17:44:31 +0200 Message-Id: <20210819154436.117798-1-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org All existing boards with sifive,e51 and sifive,u54-mc use it on top of sifive,rocket0 compatible: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed: ['sifive,e51', 'sifive,rocket0', 'riscv'] is too long Additional items are not allowed ('riscv' was unexpected) Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected) 'riscv' was expected Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index e534f6a7cfa1..aa5fb64d57eb 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -31,9 +31,7 @@ properties: - sifive,bullet0 - sifive,e5 - sifive,e7 - - sifive,e51 - sifive,e71 - - sifive,u54-mc - sifive,u74-mc - sifive,u54 - sifive,u74 @@ -41,6 +39,12 @@ properties: - sifive,u7 - canaan,k210 - const: riscv + - items: + - enum: + - sifive,e51 + - sifive,u54-mc + - const: sifive,rocket0 + - const: riscv - const: riscv # Simulator only description: Identifies that the hart uses the RISC-V instruction set