From patchwork Sat Aug 14 13:55:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 497179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3889C4320E for ; Sat, 14 Aug 2021 13:55:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8A24160F51 for ; Sat, 14 Aug 2021 13:55:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238570AbhHNN4F (ORCPT ); Sat, 14 Aug 2021 09:56:05 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:23701 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S238551AbhHNN4E (ORCPT ); Sat, 14 Aug 2021 09:56:04 -0400 X-IronPort-AV: E=Sophos;i="5.84,321,1620658800"; d="scan'208";a="90627093" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Aug 2021 22:55:35 +0900 Received: from localhost.localdomain (unknown [10.226.92.7]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9518A4272039; Sat, 14 Aug 2021 22:55:33 +0900 (JST) From: Biju Das To: Rob Herring Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 2/2] arm64: dts: renesas: r9a07g044: Add SSI support Date: Sat, 14 Aug 2021 14:55:26 +0100 Message-Id: <20210814135526.15561-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210814135526.15561-1-biju.das.jz@bp.renesas.com> References: <20210814135526.15561-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add SSI{0,1,2,3} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 6bbf1fae8ca5..c8b517d235e3 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -92,6 +92,86 @@ #size-cells = <2>; ranges; + ssi0: ssi@10049c00 { + compatible = "renesas,r9a07g044-ssi", + "renesas,rz-ssi"; + reg = <0 0x10049c00 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, + <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, + <&audio_clk1>, + <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G044_SSI0_RST_M2_REG>; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi1: ssi@1004a000 { + compatible = "renesas,r9a07g044-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>, + <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>, + <&audio_clk1>, + <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G044_SSI1_RST_M2_REG>; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi2: ssi@1004a400 { + compatible = "renesas,r9a07g044-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>, + <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>, + <&audio_clk1>, + <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G044_SSI2_RST_M2_REG>; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi3: ssi@1004a800 { + compatible = "renesas,r9a07g044-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a800 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>, + <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>, + <&audio_clk1>, + <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G044_SSI3_RST_M2_REG>; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g044"; reg = <0 0x1004b800 0 0x400>;