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Tue, 10 Aug 2021 06:17:56 +0000 From: Jacky Bai To: shawnguo@kernel.org, robh+dt@kernel.org, abel.vesa@nxp.com, sboyd@kernel.org, s.hauer@pengutronix.de, p.zabel@pengutronix.de Cc: kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org Subject: [PATCH v2 4/9] clk: imx: disable i.mx7ulp composite clock during initialization Date: Tue, 10 Aug 2021 14:28:15 +0800 Message-Id: <20210810062820.1062884-5-ping.bai@nxp.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210810062820.1062884-1-ping.bai@nxp.com> References: <20210810062820.1062884-1-ping.bai@nxp.com> X-ClientProxiedBy: SG2PR04CA0156.apcprd04.prod.outlook.com (2603:1096:4::18) To DBBPR04MB7930.eurprd04.prod.outlook.com (2603:10a6:10:1ea::12) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.71) by SG2PR04CA0156.apcprd04.prod.outlook.com (2603:1096:4::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4394.15 via Frontend Transport; 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It will cause clock HW status mismatch with clock tree info and lead to function issue. Below is an example: usdhc0's pcc clock value is 0xC5000000 during kernel boot up, it means usdhc0 clock is enabled, its parent is APLL_PFD1. In DT file, the usdhc0 clock settings are as below: assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; when kernel boot up, the clock tree info is as below, but the usdhc0 PCC register is still 0xC5000000, which means its parent is still from APLL_PFD1, which is incorrect and cause usdhc0 NOT work. nic1_clk 2 2 0 176000000 0 0 50000 usdhc0 0 0 0 176000000 0 0 50000 After making sure the peripheral clock is disabled during clock tree initialization, the usdhc0 is working, and this change is necessary for all i.MX7ULP peripheral clocks. Signed-off-by: Anson Huang --- v2 changes: no --- drivers/clk/imx/clk-composite-7ulp.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c index 9298bca7a62a..ba48445a0007 100644 --- a/drivers/clk/imx/clk-composite-7ulp.c +++ b/drivers/clk/imx/clk-composite-7ulp.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "clk.h" @@ -72,6 +73,7 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name, struct clk_gate *gate = NULL; struct clk_mux *mux = NULL; struct clk_hw *hw; + u32 val; if (mux_present) { mux = kzalloc(sizeof(*mux), GFP_KERNEL); @@ -110,6 +112,18 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name, gate_hw = &gate->hw; gate->reg = reg; gate->bit_idx = PCG_CGC_SHIFT; + /* + * make sure clock is gated during clock tree initialization, + * the HW ONLY allow clock parent/rate changed with clock gated, + * during clock tree initialization, clocks could be enabled + * by bootloader, so the HW status will mismatch with clock tree + * prepare count, then clock core driver will allow parent/rate + * change since the prepare count is zero, but HW actually + * prevent the parent/rate change due to the clock is enabled. + */ + val = readl_relaxed(reg); + val &= ~(1 << PCG_CGC_SHIFT); + writel_relaxed(val, reg); } hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,