From patchwork Tue Aug 10 05:38:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathew McBride X-Patchwork-Id: 494318 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:396:0:0:0:0 with SMTP id y22csp3608044jap; Mon, 9 Aug 2021 22:39:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyWsNTjzpRBlsGkRMvtWy73jS36l+rNVazmdtZsmJse7VyjKW0MXtsnSFDZJY1euEJHvbet X-Received: by 2002:a02:2a07:: with SMTP id w7mr25711402jaw.96.1628573990873; Mon, 09 Aug 2021 22:39:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628573990; cv=none; d=google.com; s=arc-20160816; b=zaJFz7TIF3mhkd15lz85whcM9U90ANuL7yvN/CEWzf9SAv/5qVS+8XPgJ/q0hij4WL XRpEHUcbcziSF002xrgQJWrBL7Z1xlYc+TyTfoiAWYj1Lo+zt8lH1m8H2RCWuk72EWYJ 8kwa19ZLDN2/gpZWPWxr8kzuIqQ/8H9cL2KBfjervYZMGlYvk0LIWAJAVSovXrIw9vPI QIysXbVcQRAW6JhUT0DIoFQ+h7SW919JIsLsiZLsSb8O+rL8S9USPCGaDnxcAJ//jqru ZCZRt77FxZBydqy8cnsNUaTFdzA034p08VqsZCspbg6jsaybNpPjhMQDSit/B7BWU8Ap VhsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-signature; bh=fHLUQKONyTzKMyrvQLlJZ6al0PowIRrDYxVa5ruwTlo=; b=KVcNBxQ18bsvU4g3Bfgl2XlWm3Tut7HmEcMlgrZFQOiGN31XdL012tNqt8aIJsM789 wrsWpVkEUWhkxQL0J7naADMigGHCrKfhxtSiMN2dZWT3dJZg8yP02Q8INH5U4YJKk4tK jH1WmPb4VJk6n3p6ahpP17wkcgF+0lccfqB0ZBJBwYTZlrEU+SsdWJZSgSGTAdA9G6Nl hDQU+jo6VGWqxIYvPBSITzBNAz3JxTGTt9unpn9Z6GO/DJI3WLtNcY0m0ckNgqmJZD3n E1aC5vVZWLZiYpLt4P3V2gY3116XKt/c9IRckAW5ihi/X151F74vfS+MtyyycgV9W8KQ HUmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@traverse.com.au header.s=fm1 header.b=5ZGQDGJG; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=s3riA6Jc; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p23si10078720jal.44.2021.08.09.22.39.50; Mon, 09 Aug 2021 22:39:50 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@traverse.com.au header.s=fm1 header.b=5ZGQDGJG; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=s3riA6Jc; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237204AbhHJFkL (ORCPT + 7 others); Tue, 10 Aug 2021 01:40:11 -0400 Received: from out4-smtp.messagingengine.com ([66.111.4.28]:60577 "EHLO out4-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237645AbhHJFkK (ORCPT ); Tue, 10 Aug 2021 01:40:10 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 210305C00D1; Tue, 10 Aug 2021 01:39:49 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Tue, 10 Aug 2021 01:39:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=traverse.com.au; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm1; bh=fHLUQKONyTzKM yrvQLlJZ6al0PowIRrDYxVa5ruwTlo=; b=5ZGQDGJGDTWgOGwB09OyBD3Yg7M8h Ew/+QNzgHdG41ZvAc7RHnvm3t2fQSK6vYqXK7DPMDNReimqv2pKZVdyK4N0aZo4R 8DA0bxpeNwpeDR+ZZGSzJMOhffSy+m/C3K1EnuD3SkvHYQ9vYlJJstkhRLQVuUOR 6oPZHqNtiQnjEcMI1JZ6+EL6N6PBlxC+M1z30FD1EmCpqf6MVtC9czFliIImH2Tj fozcDTAaiOCEKbaIspiWLs4cDRMJGXJqqV2DnJLprIM7DXg6rPqIfXhtANuJC3Dj CigtfuHNZ/QXTm2/C4R2qsaRGQ7dBGJVV1f3gQ7bkZQEOtRI9YBNwBpWA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=fHLUQKONyTzKMyrvQLlJZ6al0PowIRrDYxVa5ruwTlo=; b=s3riA6Jc H1tDNLVLlMJafVxTQnpYebB6I9VSPtH4sp/T/JVqmoh95FDcKkRe0FoNgFSkJVWK HD+9xyVoikXQNE+vqvLvoGo2FpoAPLfjQbxRP0uQaM6gck8UxueQ27Wsb3Lw1Hzc BRX+yF5jsT51Y6RN/1wc08X63JDkrz/sadbgtofUjGXSZYxGfN6CUd2uKxXHmqVN fuq1/kH3G85QwWJZ/E7vTgHOe30joHHIbGB2wkut7yj9heTZ2/0VhRcaCpdl+b/S eRv2bvekK9BsIgh+Sdh/aeLncLzY30JATQVYeiC6/smSScj5hTEqUOMlGvnAY1M4 ij5o54rdTh7WGQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrjeekgdellecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepofgrthhhvgif ucfotgeurhhiuggvuceomhgrthhtsehtrhgrvhgvrhhsvgdrtghomhdrrghuqeenucggtf frrghtthgvrhhnpeektdfhjeelfeeludetueevkedvvdeivdelkeevudegkeejleejvdeg kedtfeetteenucffohhmrghinhepthhrrghvvghrshgvrdgtohhmrdgruhenucevlhhush htvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehmrghtthesthhrrghv vghrshgvrdgtohhmrdgruh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 10 Aug 2021 01:39:46 -0400 (EDT) From: Mathew McBride To: Shawn Guo , Li Yang , Ioana Ciornei , Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Mathew McBride Subject: [PATCH v3 5/5] arm64: dts: add device tree for Traverse Ten64 (LS1088A) Date: Tue, 10 Aug 2021 05:38:28 +0000 Message-Id: <20210810053828.4240-6-matt@traverse.com.au> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210810053828.4240-1-matt@traverse.com.au> References: <20210722042450.11862-1-matt@traverse.com.au> <20210810053828.4240-1-matt@traverse.com.au> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Traverse Technologies Ten64 is a Mini-ITX form factor networking board using the NXP LS1088A SoC. This device tree only describes features which the mainline kernel currently has support for, such as some I2C-connected devices that are not described at present. System documentation may be found at ten64doc.traverse.com.au Signed-off-by: Mathew McBride Reviewed-by: Ioana Ciornei # for the MAC/PHY --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/fsl-ls1088a-ten64.dts | 389 ++++++++++++++++++ 2 files changed, 390 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts -- 2.30.1 diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 25806c4924cb..2b3ee42e4a2a 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -19,6 +19,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts new file mode 100644 index 000000000000..3063851c2fb9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Travese Ten64 (LS1088) board + * Based on fsl-ls1088a-rdb.dts + * Copyright 2017-2020 NXP + * Copyright 2019-2021 Traverse Technologies + * + * Author: Mathew McBride + */ + +/dts-v1/; + +#include "fsl-ls1088a.dtsi" + +#include +#include + +/ { + model = "Traverse Ten64"; + compatible = "traverse,ten64", "fsl,ls1088a"; + + aliases { + serial0 = &duart0; + serial1 = &duart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + buttons { + compatible = "gpio-keys"; + + /* Fired by system controller when + * external power off (e.g ATX Power Button) + * asserted + */ + powerdn { + label = "External Power Down"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + interrupts = <&gpio1 17 IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + }; + + /* Rear Panel 'ADMIN' button (GPIO_H) */ + admin { + label = "ADMIN button"; + gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + interrupts = <&gpio3 8 IRQ_TYPE_EDGE_RISING>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + sfp1down { + label = "ten64:green:sfp1:down"; + gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; + }; + + sfp2up { + label = "ten64:green:sfp2:up"; + gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + }; + + admin { + label = "ten64:admin"; + gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>; + }; + }; + + sfp_xg0: dpmac2-sfp { + compatible = "sff,sfp"; + i2c-bus = <&sfplower_i2c>; + tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>; + los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <2000>; + }; + + sfp_xg1: dpmac1-sfp { + compatible = "sff,sfp"; + i2c-bus = <&sfpupper_i2c>; + tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>; + los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <2000>; + }; +}; + +/* XG1 - Upper SFP */ +&dpmac1 { + sfp = <&sfp_xg1>; + pcs-handle = <&pcs1>; + phy-connection-type = "10gbase-r"; + managed = "in-band-status"; +}; + +/* XG0 - Lower SFP */ +&dpmac2 { + sfp = <&sfp_xg0>; + pcs-handle = <&pcs2>; + phy-connection-type = "10gbase-r"; + managed = "in-band-status"; +}; + +/* DPMAC3..6 is GE4 to GE8 */ +&dpmac3 { + phy-handle = <&mdio1_phy5>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs3_0>; +}; + +&dpmac4 { + phy-handle = <&mdio1_phy6>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs3_1>; +}; + +&dpmac5 { + phy-handle = <&mdio1_phy7>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs3_2>; +}; + +&dpmac6 { + phy-handle = <&mdio1_phy8>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs3_3>; +}; + +/* DPMAC7..10 is GE0 to GE3 */ +&dpmac7 { + phy-handle = <&mdio1_phy1>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs7_0>; +}; + +&dpmac8 { + phy-handle = <&mdio1_phy2>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs7_1>; +}; + +&dpmac9 { + phy-handle = <&mdio1_phy3>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs7_2>; +}; + +&dpmac10 { + phy-handle = <&mdio1_phy4>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs7_3>; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&emdio1 { + status = "okay"; + + mdio1_phy5: ethernet-phy@c { + reg = <0xc>; + }; + + mdio1_phy6: ethernet-phy@d { + reg = <0xd>; + }; + + mdio1_phy7: ethernet-phy@e { + reg = <0xe>; + }; + + mdio1_phy8: ethernet-phy@f { + reg = <0xf>; + }; + + mdio1_phy1: ethernet-phy@1c { + reg = <0x1c>; + }; + + mdio1_phy2: ethernet-phy@1d { + reg = <0x1d>; + }; + + mdio1_phy3: ethernet-phy@1e { + reg = <0x1e>; + }; + + mdio1_phy4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; + +&esdhc { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + sfpgpio: gpio@76 { + compatible = "ti,tca9539"; + reg = <0x76>; + #gpio-cells = <2>; + gpio-controller; + + admin_led_lower { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-low; + }; + }; + + at97sc: tpm@29 { + compatible = "atmel,at97sc3204t"; + reg = <0x29>; + }; +}; + +&i2c2 { + status = "okay"; + + rx8035: rtc@32 { + compatible = "epson,rx8035"; + reg = <0x32>; + }; +}; + +&i2c3 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9540"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + sfpupper_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + sfplower_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; +}; + +&pcs_mdio1 { + status = "okay"; +}; + +&pcs_mdio2 { + status = "okay"; +}; + +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio7 { + status = "okay"; +}; + +&qspi { + status = "okay"; + + en25s64: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <20000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0 0x100000>; + }; + + partition@100000 { + label = "bl3"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "mcfirmware"; + reg = <0x300000 0x200000>; + }; + + partition@500000 { + label = "ubootenv"; + reg = <0x500000 0x80000>; + }; + + partition@580000 { + label = "dpl"; + reg = <0x580000 0x40000>; + }; + + partition@5C0000 { + label = "dpc"; + reg = <0x5C0000 0x40000>; + }; + + partition@600000 { + label = "devicetree"; + reg = <0x600000 0x40000>; + }; + }; + }; + + nand: flash@1 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <1>; + spi-max-frequency = <20000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* reserved for future boot direct from NAND flash + * (this would use the same layout as the 8MiB NOR flash) + */ + partition@0 { + label = "nand-boot-reserved"; + reg = <0 0x800000>; + }; + + /* recovery / install environment */ + partition@800000 { + label = "recovery"; + reg = <0x800000 0x2000000>; + }; + + /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */ + partition@2800000 { + label = "ubia"; + reg = <0x2800000 0x6C00000>; + }; + + /* ubib (second OpenWrt) */ + partition@9400000 { + label = "ubib"; + reg = <0x9400000 0x6C00000>; + }; + }; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +};