From patchwork Tue Aug 3 07:59:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 491117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83A6CC43214 for ; Tue, 3 Aug 2021 07:59:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 706896103C for ; Tue, 3 Aug 2021 07:59:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234232AbhHCH7o (ORCPT ); Tue, 3 Aug 2021 03:59:44 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:41100 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234393AbhHCH7j (ORCPT ); Tue, 3 Aug 2021 03:59:39 -0400 X-UUID: 014efde1c4004d7abdf21f89334cdf9d-20210803 X-UUID: 014efde1c4004d7abdf21f89334cdf9d-20210803 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 580928158; Tue, 03 Aug 2021 15:59:26 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 3 Aug 2021 15:59:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 3 Aug 2021 15:59:24 +0800 From: Tinghan Shen To: , , , , , , , , , , , , CC: , , , , , Tinghan Shen Subject: [PATCH v5 5/5] remoteproc: mediatek: Support mt8195 scp Date: Tue, 3 Aug 2021 15:59:22 +0800 Message-ID: <20210803075922.11611-6-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210803075922.11611-1-tinghan.shen@mediatek.com> References: <20210803075922.11611-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SCP clock design is changed on mt8195 that doesn't need to control SCP clock on kernel side. Signed-off-by: Tinghan Shen Reviewed-by: Mathieu Poirier --- drivers/remoteproc/mtk_common.h | 1 + drivers/remoteproc/mtk_scp.c | 48 +++++++++++++++++++++++++++++---- 2 files changed, 44 insertions(+), 5 deletions(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index 61901f5efa05..5ff3867c72f3 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -72,6 +72,7 @@ struct scp_ipi_desc { struct mtk_scp; struct mtk_scp_of_data { + int (*scp_clk_get)(struct mtk_scp *scp); int (*scp_before_load)(struct mtk_scp *scp); void (*scp_irq_handler)(struct mtk_scp *scp); void (*scp_reset_assert)(struct mtk_scp *scp); diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 9679cc26895e..36e48cf58ed6 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -312,6 +312,32 @@ static int scp_elf_read_ipi_buf_addr(struct mtk_scp *scp, return -ENOENT; } +static int mt8183_scp_clk_get(struct mtk_scp *scp) +{ + struct device *dev = scp->dev; + int ret = 0; + + scp->clk = devm_clk_get(dev, "main"); + if (IS_ERR(scp->clk)) { + dev_err(dev, "Failed to get clock\n"); + ret = PTR_ERR(scp->clk); + } + + return ret; +} + +static int mt8192_scp_clk_get(struct mtk_scp *scp) +{ + return mt8183_scp_clk_get(scp); +} + +static int mt8195_scp_clk_get(struct mtk_scp *scp) +{ + scp->clk = NULL; + + return 0; +} + static int mt8183_scp_before_load(struct mtk_scp *scp) { /* Clear SCP to host interrupt */ @@ -785,12 +811,9 @@ static int scp_probe(struct platform_device *pdev) if (ret) goto destroy_mutex; - scp->clk = devm_clk_get(dev, "main"); - if (IS_ERR(scp->clk)) { - dev_err(dev, "Failed to get clock\n"); - ret = PTR_ERR(scp->clk); + ret = scp->data->scp_clk_get(scp); + if (ret) goto release_dev_mem; - } /* register SCP initialization IPI */ ret = scp_ipi_register(scp, SCP_IPI_INIT, scp_init_ipi_handler, scp); @@ -852,6 +875,7 @@ static int scp_remove(struct platform_device *pdev) } static const struct mtk_scp_of_data mt8183_of_data = { + .scp_clk_get = mt8183_scp_clk_get, .scp_before_load = mt8183_scp_before_load, .scp_irq_handler = mt8183_scp_irq_handler, .scp_reset_assert = mt8183_scp_reset_assert, @@ -864,6 +888,19 @@ static const struct mtk_scp_of_data mt8183_of_data = { }; static const struct mtk_scp_of_data mt8192_of_data = { + .scp_clk_get = mt8192_scp_clk_get, + .scp_before_load = mt8192_scp_before_load, + .scp_irq_handler = mt8192_scp_irq_handler, + .scp_reset_assert = mt8192_scp_reset_assert, + .scp_reset_deassert = mt8192_scp_reset_deassert, + .scp_stop = mt8192_scp_stop, + .scp_da_to_va = mt8192_scp_da_to_va, + .host_to_scp_reg = MT8192_GIPC_IN_SET, + .host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT, +}; + +static const struct mtk_scp_of_data mt8195_of_data = { + .scp_clk_get = mt8195_scp_clk_get, .scp_before_load = mt8192_scp_before_load, .scp_irq_handler = mt8192_scp_irq_handler, .scp_reset_assert = mt8192_scp_reset_assert, @@ -877,6 +914,7 @@ static const struct mtk_scp_of_data mt8192_of_data = { static const struct of_device_id mtk_scp_of_match[] = { { .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data }, { .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data }, + { .compatible = "mediatek,mt8195-scp", .data = &mt8195_of_data }, {}, }; MODULE_DEVICE_TABLE(of, mtk_scp_of_match);