From patchwork Fri Jul 30 14:49:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 489465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBAF0C19F37 for ; Fri, 30 Jul 2021 14:50:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C1F0A60EFD for ; Fri, 30 Jul 2021 14:50:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231220AbhG3OuN (ORCPT ); Fri, 30 Jul 2021 10:50:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239559AbhG3OuD (ORCPT ); Fri, 30 Jul 2021 10:50:03 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FA4FC0612E8 for ; Fri, 30 Jul 2021 07:49:40 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id x14so13518382edr.12 for ; Fri, 30 Jul 2021 07:49:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tQGRmp6w/PSekRXBpdFwg0L2q55A125G3jOg4JhNBfI=; b=K2aZWGktsgMltZ3WLzBixgOfIHWcImbQSJya4GM1UG4HTCccAN1gtNKZdXnDZa6xs7 Q8SkI6yYdX+gWCzQAhq9hY1d0wvUlH9k3nueLL5Hxfjtt7Cf6MZrLGDzjshOdHQhIKcb eVglYOajtTjQAP8vR+xbsgEYdgpMfCVbVtitIdzAI7m8eb1UO9NAuGE9jFgkXTzX47bw KaTKRkMRrhDZpGkLFHXOk9vPLbemW1gt41649JDo51nymBKJ/0kzYYMgU8AvXnclNOB+ tpo22Hl7+hPbldDb4DhfGH1Ji4VRwSBYiYtptEjFhlcn/W8RRVQ6I58JDN3e60h4dQHu y1kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tQGRmp6w/PSekRXBpdFwg0L2q55A125G3jOg4JhNBfI=; b=mT68R+pwjBz3nqV12ksp4mSwGYHKmzSXKJGxe9NHc1aS1mAIdNAgQIuUecsWAUtf8q 06CrIByJCijBXVDyYRk3HYnZ9HHs6o6gOoplBWRHtcVcW33/rDBbFTKDzbrE/gIgA5Ni IE9gjJU0uBGQuTs5f+pyO9uoeC0iP5Aux5urecpi7roNCACIDWgt3DU+LD4gytrlcuqT fK8YbVkeVQ/Kbwi00cJC6Ax0kwzgfUpaSHQkTCiRLVAUOg4O7LjgAKbMr6tE0h6p8+HN bu5n/Ov+3N5yn3eQzsc5iKThp7++ddlRpEVQ2hA2HR6Hh5FJLNvZNVWi7l3WWo8dodmc iBQQ== X-Gm-Message-State: AOAM533PN+kYyym0Zc6l82EYfrF8VC6UdmWqbiJz/Bjs7AhFzJ7gytR1 3n85N2dYMLtxuZcF+qGABJdbFg== X-Google-Smtp-Source: ABdhPJxn0sgrAzc8oH2ckgTDzHk+Zg1E5gqFm4yp+FA/Rh9DceW9eF7J/ZELRVS4eClsIdsbkum/UA== X-Received: by 2002:a05:6402:26ca:: with SMTP id x10mr3404671edd.319.1627656579080; Fri, 30 Jul 2021 07:49:39 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id p18sm783100edu.8.2021.07.30.07.49.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 07:49:38 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa Cc: Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 10/12] clk: samsung: Add Exynos850 clock driver stub Date: Fri, 30 Jul 2021 17:49:20 +0300 Message-Id: <20210730144922.29111-11-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For now it's just a stub driver to make serial driver work. Later it will be implemented properly. This driver doesn't really change clocks, only registers the UART clock as a fixed-rate clock. Without this clock driver the UART driver won't work, as it's trying to obtain "uart" clock and fails if it's not able to. From drivers/tty/serial/samsung_tty.c: 8<------------------------------------------------------------------->8 ourport->clk = clk_get(&platdev->dev, "uart"); if (IS_ERR(ourport->clk)) { pr_err("%s: Controller clock not found\n", dev_name(&platdev->dev)); ret = PTR_ERR(ourport->clk); goto err; } 8<------------------------------------------------------------------->8 In order to get functional serial console we have to implement that minimal clock driver with "uart" clock. It's not necessary to actually configure clocks, as those are already configured in bootloader, so kernel can rely on that for now. 80 column limit is broken here to make checkpatch happy, otherwise it swears about incorrect __initconst usage. Signed-off-by: Sam Protsenko --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos850.c | 63 +++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos850.c diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 028b2e27a37e..c46cf11e4d0b 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c new file mode 100644 index 000000000000..3192ec9bb90b --- /dev/null +++ b/drivers/clk/samsung/clk-exynos850.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Common Clock Framework support for Exynos850 SoC. + */ + +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +/* Fixed rate clocks generated outside the SoC */ +static struct samsung_fixed_rate_clock exynos850_fixed_rate_ext_clks[] __initdata = { + FRATE(OSCCLK, "fin_pll", NULL, 0, 26000000), +}; + +/* + * Model the UART clock as a fixed-rate clock for now, to make serial driver + * work. This clock is already configured in the bootloader. + */ +static const struct samsung_fixed_rate_clock exynos850_peri_clks[] __initconst = { + FRATE(DOUT_UART, "DOUT_UART", NULL, 0, 200000000), +}; + +static const struct of_device_id ext_clk_match[] __initconst = { + { .compatible = "samsung,exynos850-oscclk", .data = (void *)0 }, + {}, +}; + +void __init exynos850_clk_init(struct device_node *np) +{ + void __iomem *reg_base; + struct samsung_clk_provider *ctx; + + if (!np) + panic("%s: unable to determine soc\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); + if (!ctx) + panic("%s: unable to allocate ctx\n", __func__); + + samsung_clk_of_register_fixed_ext(ctx, + exynos850_fixed_rate_ext_clks, + ARRAY_SIZE(exynos850_fixed_rate_ext_clks), + ext_clk_match); + + samsung_clk_register_fixed_rate(ctx, exynos850_peri_clks, + ARRAY_SIZE(exynos850_peri_clks)); + + samsung_clk_of_add_provider(np, ctx); +} + +CLK_OF_DECLARE(exynos850_clk, "samsung,exynos850-clock", exynos850_clk_init);