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Wed, 28 Jul 2021 16:11:29 +0000 From: Michael Riesch To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Rob Herring , Heiko Stuebner , Liang Chen , Peter Geis , Michael Riesch , Simon Xue Subject: [PATCH 2/2] arm64: dts: rockchip: rk3568-evb1-v10: add ethernet support Date: Wed, 28 Jul 2021 18:10:20 +0200 Message-Id: <20210728161020.3905-3-michael.riesch@wolfvision.net> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210728161020.3905-1-michael.riesch@wolfvision.net> References: <20210728161020.3905-1-michael.riesch@wolfvision.net> X-ClientProxiedBy: AM6PR0502CA0068.eurprd05.prod.outlook.com (2603:10a6:20b:56::45) To DBBPR08MB4523.eurprd08.prod.outlook.com (2603:10a6:10:c8::19) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from carlos.wolfvision-at.intra (91.118.163.37) by AM6PR0502CA0068.eurprd05.prod.outlook.com (2603:10a6:20b:56::45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4373.18 via Frontend Transport; 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compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568"; + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; + chosen: chosen { stdout-path = "serial2:1500000n8"; }; @@ -67,6 +72,70 @@ }; }; +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x3c>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reg = <0x0>; + }; +}; + &sdhci { bus-width = <8>; max-frequency = <200000000>;