From patchwork Tue Jul 27 16:11:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 486910 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5000C4338F for ; Tue, 27 Jul 2021 16:11:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A73BD61B73 for ; Tue, 27 Jul 2021 16:11:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229596AbhG0QLO (ORCPT ); Tue, 27 Jul 2021 12:11:14 -0400 Received: from finn.gateworks.com ([108.161.129.64]:58966 "EHLO finn.localdomain" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229540AbhG0QLN (ORCPT ); Tue, 27 Jul 2021 12:11:13 -0400 Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1m8Pff-005DjI-9s; Tue, 27 Jul 2021 16:11:07 +0000 From: Tim Harvey To: Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Tim Harvey Subject: [PATCH 5/5] arm64: dts: imx8mm-venice-gw7901: enable pull-down on gpio outputs Date: Tue, 27 Jul 2021 09:11:01 -0700 Message-Id: <20210727161101.32267-5-tharvey@gateworks.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210727161101.32267-1-tharvey@gateworks.com> References: <20210727161101.32267-1-tharvey@gateworks.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable internal pull-down on UART transceiver GPIO config pins. Signed-off-by: Tim Harvey --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index db43ee28bdb6..0216facb2aef 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -877,9 +877,9 @@ pinctrl_uart3_gpio: uart3gpiogrp { fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000041 /* RS232# */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* RS422# */ - MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000041 /* RS485# */ + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */ + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */ + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */ >; };