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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id q20sm872910otv.50.2021.07.24.21.02.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jul 2021 21:02:26 -0700 (PDT) From: Bjorn Andersson To: Bjorn Helgaas , Rob Herring , Stanimir Varbanov , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wil?= =?utf-8?q?czy=C5=84ski?= Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] PCI: qcom: Split init and enable for 1.9.0 and 2.7.0 Date: Sat, 24 Jul 2021 21:00:37 -0700 Message-Id: <20210725040038.3966348-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210725040038.3966348-1-bjorn.andersson@linaro.org> References: <20210725040038.3966348-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On the sc8180x platform the "msi" interrupt often fires before init has a chance to enable the clocks that are necessary for the interrupt handler to access the hardware. Split out the resource enablement and disablement into the newly introduce enable/disable resource operations, to ensure that the necessary resources are enabled when needed. Signed-off-by: Bjorn Andersson --- drivers/pci/controller/dwc/pcie-qcom.c | 31 +++++++++++++++++--------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8a64a126de2b..8adcbb718832 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1173,12 +1173,11 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) return PTR_ERR_OR_ZERO(res->pipe_clk); } -static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) +static int qcom_pcie_enable_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; - u32 val; int ret; ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); @@ -1211,6 +1210,20 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) goto err_disable_clocks; } + return 0; + +err_disable_clocks: + clk_bulk_disable_unprepare(res->num_clks, res->clks); +err_disable_regulators: + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + + return ret; +} + +static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) +{ + u32 val; + /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); @@ -1238,15 +1251,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) } return 0; -err_disable_clocks: - clk_bulk_disable_unprepare(res->num_clks, res->clks); -err_disable_regulators: - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - - return ret; } -static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) +static void qcom_pcie_disable_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; @@ -1465,8 +1472,9 @@ static const struct qcom_pcie_ops ops_2_3_3 = { /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */ static const struct qcom_pcie_ops ops_2_7_0 = { .get_resources = qcom_pcie_get_resources_2_7_0, + .enable_resources = qcom_pcie_enable_2_7_0, .init = qcom_pcie_init_2_7_0, - .deinit = qcom_pcie_deinit_2_7_0, + .disable_resources = qcom_pcie_disable_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .post_init = qcom_pcie_post_init_2_7_0, .post_deinit = qcom_pcie_post_deinit_2_7_0, @@ -1475,8 +1483,9 @@ static const struct qcom_pcie_ops ops_2_7_0 = { /* Qcom IP rev.: 1.9.0 */ static const struct qcom_pcie_ops ops_1_9_0 = { .get_resources = qcom_pcie_get_resources_2_7_0, + .enable_resources = qcom_pcie_enable_2_7_0, .init = qcom_pcie_init_2_7_0, - .deinit = qcom_pcie_deinit_2_7_0, + .disable_resources = qcom_pcie_disable_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .post_init = qcom_pcie_post_init_2_7_0, .post_deinit = qcom_pcie_post_deinit_2_7_0,