| Message ID | 20210723214031.3251801-6-atish.patra@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Support non-coherent DMA on RISC-V using a global pool | expand |
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8fcceb8eda07..931b283c8ec9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -209,6 +209,14 @@ config PGTABLE_LEVELS config LOCKDEP_SUPPORT def_bool y +config RISCV_DMA_NONCOHERENT + bool + select ARCH_HAS_DMA_PREP_COHERENT + select ARCH_HAS_SYNC_DMA_FOR_DEVICE + select ARCH_HAS_SYNC_DMA_FOR_CPU + select ARCH_HAS_SETUP_DMA_OPS + select DMA_GLOBAL_POOL + source "arch/riscv/Kconfig.socs" source "arch/riscv/Kconfig.erratas"
In future, there will be more RISC-V platforms with non-coherent DMA. Instead of selecting all the required config options in every soc, create a new config that selects all the required configs related non-coherent DMA. Signed-off-by: Atish Patra <atish.patra@wdc.com> --- arch/riscv/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+)