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[23.128.96.18]) by mx.google.com with ESMTP id u15si18586418iot.89.2021.07.18.03.49.20; Sun, 18 Jul 2021 03:49:20 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zpvRKC8F; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233082AbhGRKwO (ORCPT + 7 others); Sun, 18 Jul 2021 06:52:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232851AbhGRKwM (ORCPT ); Sun, 18 Jul 2021 06:52:12 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E735BC0613DD for ; Sun, 18 Jul 2021 03:49:13 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id l11so5958843ljq.4 for ; Sun, 18 Jul 2021 03:49:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lYWJNz4RjhdOK3xgOEToM1HEgwLI9uBrUK4vDt0ZL48=; b=zpvRKC8FyYNchdzHLterZZRcnXOibDPnmrNJbeuyo3fw3zuEhDgQCJ0dpuJpARUqyT NtVCUUvQTSPYP6yecupgZVu4E/yvMyP4jnDJs5OpT/Cq3CZ8pb5E0v+wVVyrvTqPopSr MRifeAA1c5W7vyNaIlPiz1Z1uSbyNF4BhY+DaVJpiRCeLALGPCRzjCpywOL82F+hjzD6 QDeh1Gs1ePASoscEhcv5Y8RXy2uJTQudBra0sJbsxOFsRsP7SaoQGaqYOYre+Y2LADpS JI+oRXfwQAj4X3bMB/izS8Z3VF39Qbusf79Ar5fy/7736ptLRmEIG99vfX3KVyymnjI9 +fvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lYWJNz4RjhdOK3xgOEToM1HEgwLI9uBrUK4vDt0ZL48=; b=DUJyju+qeC50NOpWVilqpav5mXEtP/2+/oZpicc5wjPU4iwLmQbBf+4NAGZrLurHL/ e9NyJ4G0QNqdpYkNl8Ifv7ctR90Zv2UGJSLof9tAnHB9oZru+gt/khXt3ROYp8fWlCJ9 jXbUeV+83wCYhbLjk+hpg0Abl73zDtqfIGEPilBsS12bBwIss/fzRyEZghoEybjGvNDU hKa/ILOfLkGp11CwgrecM8XyslqlefUsWmG6oL5vwsrwG4gHe5j8X4HsFetq4qw8rXK/ ACqM5xKqrFTzSSKwd/RujMdDZT/v9L8jLXFneNC2RmSJpPqVTTL4ohFl4axLBbV78Hn3 PPjw== X-Gm-Message-State: AOAM531X4kkI3qxlfEQj3MHrIh2GyWj4na3pZQ0txtE9xjsS0p1brMgq hNPm/KUPrfT2EfxxrzDuNGOpd0C+V8j2+A== X-Received: by 2002:a05:651c:1253:: with SMTP id h19mr17404671ljh.303.1626605352314; Sun, 18 Jul 2021 03:49:12 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y22sm1039528lfh.154.2021.07.18.03.49.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jul 2021 03:49:11 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v5 6/9] clk: qcom: gdsc: enable optional power domain support Date: Sun, 18 Jul 2021 13:48:58 +0300 Message-Id: <20210718104901.454843-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210718104901.454843-1-dmitry.baryshkov@linaro.org> References: <20210718104901.454843-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Currently we use a regulator to enable this domain on demand, however this has some consequences, as genpd code is not reentrant. Make gdsc code also use pm_runtime calls to ensure that registers are accessible during the gdsc_enable/gdsc_disable operations. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gdsc.c | 59 ++++++++++++++++++++++++++++++++++++++--- drivers/clk/qcom/gdsc.h | 2 ++ 2 files changed, 58 insertions(+), 3 deletions(-) -- 2.30.2 diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 51ed640e527b..a0781d7284cc 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -50,6 +51,22 @@ enum gdsc_status { GDSC_ON }; +static int gdsc_pm_runtime_get(struct gdsc *sc) +{ + if (!sc->dev) + return 0; + + return pm_runtime_resume_and_get(sc->dev); +} + +static int gdsc_pm_runtime_put(struct gdsc *sc) +{ + if (!sc->dev) + return 0; + + return pm_runtime_put_sync(sc->dev); +} + /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */ static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status) { @@ -232,9 +249,8 @@ static void gdsc_retain_ff_on(struct gdsc *sc) regmap_update_bits(sc->regmap, sc->gdscr, mask, mask); } -static int gdsc_enable(struct generic_pm_domain *domain) +static int _gdsc_enable(struct gdsc *sc) { - struct gdsc *sc = domain_to_gdsc(domain); int ret; if (sc->pwrsts == PWRSTS_ON) @@ -290,11 +306,26 @@ static int gdsc_enable(struct generic_pm_domain *domain) return 0; } -static int gdsc_disable(struct generic_pm_domain *domain) +static int gdsc_enable(struct generic_pm_domain *domain) { struct gdsc *sc = domain_to_gdsc(domain); int ret; + ret = gdsc_pm_runtime_get(sc); + if (ret) + return ret; + + ret = _gdsc_enable(sc); + + gdsc_pm_runtime_put(sc); + + return ret; +} + +static int _gdsc_disable(struct gdsc *sc) +{ + int ret; + if (sc->pwrsts == PWRSTS_ON) return gdsc_assert_reset(sc); @@ -329,6 +360,22 @@ static int gdsc_disable(struct generic_pm_domain *domain) return 0; } +static int gdsc_disable(struct generic_pm_domain *domain) +{ + struct gdsc *sc = domain_to_gdsc(domain); + int ret; + + ret = gdsc_pm_runtime_get(sc); + if (ret) + return ret; + + ret = _gdsc_disable(sc); + + gdsc_pm_runtime_put(sc); + + return ret; +} + static int gdsc_init(struct gdsc *sc) { u32 mask, val; @@ -425,6 +472,8 @@ int gdsc_register(struct gdsc_desc *desc, for (i = 0; i < num; i++) { if (!scs[i]) continue; + if (pm_runtime_enabled(dev)) + scs[i]->dev = dev; scs[i]->regmap = regmap; scs[i]->rcdev = rcdev; ret = gdsc_init(scs[i]); @@ -439,6 +488,8 @@ int gdsc_register(struct gdsc_desc *desc, continue; if (scs[i]->parent) pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd); + else if (!IS_ERR_OR_NULL(dev->pm_domain)) + pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); } return of_genpd_add_provider_onecell(dev->of_node, data); @@ -457,6 +508,8 @@ void gdsc_unregister(struct gdsc_desc *desc) continue; if (scs[i]->parent) pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd); + else if (!IS_ERR_OR_NULL(dev->pm_domain)) + pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); } of_genpd_del_provider(dev->of_node); } diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 5bb396b344d1..702d47a87af6 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -25,6 +25,7 @@ struct reset_controller_dev; * @resets: ids of resets associated with this gdsc * @reset_count: number of @resets * @rcdev: reset controller + * @dev: the device holding the GDSC, used for pm_runtime calls */ struct gdsc { struct generic_pm_domain pd; @@ -58,6 +59,7 @@ struct gdsc { const char *supply; struct regulator *rsupply; + struct device *dev; }; struct gdsc_desc {