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[23.128.96.18]) by mx.google.com with ESMTP id u15si18586418iot.89.2021.07.18.03.49.16; Sun, 18 Jul 2021 03:49:16 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t+HDcrLU; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232845AbhGRKwL (ORCPT + 7 others); Sun, 18 Jul 2021 06:52:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232851AbhGRKwJ (ORCPT ); Sun, 18 Jul 2021 06:52:09 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19E2AC061768 for ; Sun, 18 Jul 2021 03:49:10 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id g22so12368190lfu.0 for ; Sun, 18 Jul 2021 03:49:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D63/+TxRKfSO58fkCSffqgWBORWJvZPVM0amiHKwxec=; b=t+HDcrLUacRbP8DNOo5e+GGGeA4NvCD16BJ6c9ka/ZJCd3Nrv0m/OPSnhoca/L5Igj NWWteA5rbOi21sMd5M2yzB7oPIJPe1s+LlUlQTO9nibj69OR/n//T/n52ChJmo8kA1Lw Jj7WfAhY2T/S9uCN0pnCx6Y1EpU9+90hCQgo+Rqqkuz6RZ0PZiXgoprRAJ75NE5dGKWn 5Hin+Sxz3IVE5JWELvfTEFkpkjYPU6Y4+cZPS5JW83kuF9XJR/Z3aHM1UY5PBgb9lnWT tWhmhCMwLAo/Orn+ldJhB472Aanj37ZIkjs/pg3O+Eman8HYvduy0fN2WdSimiL9JFq+ XTgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D63/+TxRKfSO58fkCSffqgWBORWJvZPVM0amiHKwxec=; b=eW8ctPCWmDq+oxT37KRvdob37YBZ1EKyRcyBFzQnWDF0A0i00+kaksue+Li3yZxc4Z 0aPfEh8/EAhFWBCelSZmtHJHOtKMKQ73b8xlNu2+13+OC/hpisfjAUK9xRtUpwgmO3yz Pi7wQO0/MMhxfI7wO3hOBJdujNqubpa5fOYeZg4rRs0nG/ZhuPXk6OJ2eJURrdrJwlMU VCjBi9sXuBNtHcNdBhgxIJdfgn1A7fvHkt6MpsYSvbdA7fRAWe6K1GMsxasP1AYtHtRJ B6fadfhthdtrt2hGuaWEZlMkoSlpvBJWMKVhdVu9b5Sd6OU7iNFli1rS1ACW2uOi9uT9 4nzQ== X-Gm-Message-State: AOAM5314QA/AZMOG4vG7LBn1JGESEuAjCiv59fpMrao35OcE/vRCmORw PLtfX8qhMuum2zs5kKMF98SEHg== X-Received: by 2002:ac2:4206:: with SMTP id y6mr14382336lfh.206.1626605348335; Sun, 18 Jul 2021 03:49:08 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y22sm1039528lfh.154.2021.07.18.03.49.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jul 2021 03:49:08 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v5 1/9] dt-bindings: clock: qcom, dispcc-sm8x50: add mmcx power domain Date: Sun, 18 Jul 2021 13:48:53 +0300 Message-Id: <20210718104901.454843-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210718104901.454843-1-dmitry.baryshkov@linaro.org> References: <20210718104901.454843-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On sm8250 dispcc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 6667261dc665..6b3380cf1a10 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -56,6 +56,11 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + required: - compatible - reg @@ -70,6 +75,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0x0af00000 0x10000>; @@ -90,5 +96,6 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; }; ...