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Wed, 14 Jul 2021 14:02:10 +0000 Received: from AM9PR09MB4884.eurprd09.prod.outlook.com ([fe80::60d1:9cfe:5e26:92b5]) by AM9PR09MB4884.eurprd09.prod.outlook.com ([fe80::60d1:9cfe:5e26:92b5%6]) with mapi id 15.20.4331.022; Wed, 14 Jul 2021 14:02:10 +0000 From: Oliver Graute To: shawnguo@kernel.org Cc: devicetree@vger.kernel.org, aisheng.dong@nxp.com, oliver.graute@gmail.com, festevam@gmail.com, Oliver Graute , Rob Herring , Sascha Hauer , Sascha Hauer , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1] arm64: add lpsi1 and lpspi_lpcg to imx8-ss-dma.dtsi Date: Wed, 14 Jul 2021 15:59:35 +0200 Message-Id: <20210714135939.20403-1-oliver.graute@kococonnector.com> X-Mailer: git-send-email 2.17.1 X-ClientProxiedBy: AM4PR0902CA0011.eurprd09.prod.outlook.com (2603:10a6:200:9b::21) To AM9PR09MB4884.eurprd09.prod.outlook.com (2603:10a6:20b:281::9) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost (2.207.138.2) by AM4PR0902CA0011.eurprd09.prod.outlook.com (2603:10a6:200:9b::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; 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}; + lpspi1: lpspi@5a010000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a010000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&lpspi1_lpcg IMX_LPCG_CLK_0>, + <&lpspi1_lpcg IMX_LPCG_CLK_4>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_1>; + status = "disabled"; + }; + + lpspi1_lpcg: clock-controller@5a410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a410000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "spi1_lpcg_clk", + "spi1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_1>; + }; + uart0_lpcg: clock-controller@5a460000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a460000 0x10000>;