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[23.128.96.18]) by mx.google.com with ESMTP id j23si7548681iog.79.2021.07.09.14.07.48; Fri, 09 Jul 2021 14:07:48 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iqRjoC4s; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230418AbhGIVK2 (ORCPT + 7 others); Fri, 9 Jul 2021 17:10:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230389AbhGIVKY (ORCPT ); Fri, 9 Jul 2021 17:10:24 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2374C0613E8 for ; Fri, 9 Jul 2021 14:07:40 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id s18so10115720ljg.7 for ; Fri, 09 Jul 2021 14:07:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+RsBgnaOEY6/D9h9tw7M0512ZsXvNepWazm5EwprVZg=; b=iqRjoC4sSD7JA2u5vPh98B8Q4dAjSCJKj32PG2lYW1fjpvKOO22OeHIGHwaJA6u2a5 bdhYN2a0TlRCHFjfRHkDiq+0H1AHzHEH4sZTqnlFYKQml2IWb+WTllFSb8O+5aNxrX8X V78Tq/di6jrUycafAC9jEtRS9+Zimsda1MJBBjBmu18Bv9+AlF8LIWcG9Y8MmxvCDO00 QnGcEQvl1oo4VgcRVpzH58nsSYjgTQ9f4rr0nk67tdxzFTSfvpJ/Yn93z0FC7LGEyx+I Uh9w29xgwymYox4l65aIa3BBsiBX8RFxjBI+n1ChgClkGkFybRMOIoJkAOqrfFiCYEiI SQSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+RsBgnaOEY6/D9h9tw7M0512ZsXvNepWazm5EwprVZg=; b=I6S83PndV3HdJEF6h+NXirP+6auNJHZGpsegSkqX8+n7OJWp4DOwpf95iU1tj6dRFJ lxqjg2qhWxRVeQBA1om/8D3Gx9lV0AhAgZOElLr2jXqgf6f47wTXp4oQU0L4+jORZOxu 6DufyZhjRHJ93Rn8sv943iFkH9JSS1BJ7IZmzsYit/PsRdpQsB29CaqQNZ0oTw/LjfBK HhLHuxB9iKFU+/zl/NNRqJXkTCzpHQSl8pstKkTr9OH714SH2cKRyckUga9e2XT9cB7Z yv8qBlMHvw4IFQYjJI4ByjJMiGKmgUgDtJ5Tzfscq2zxifsFWSCMYMg9g8tnurivnd2i t4qQ== X-Gm-Message-State: AOAM5329QThMlPhoUN1w+wNJfGzbN67B3UbkK5w4EcYCLerLMxDCLNTv JyfIUrVLJk/VoA+TEC6PhLlvQw== X-Received: by 2002:a05:651c:10b2:: with SMTP id k18mr20391724ljn.228.1625864859232; Fri, 09 Jul 2021 14:07:39 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id n15sm590625lfh.70.2021.07.09.14.07.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 14:07:38 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 8/8] drm/msm/dsi: drop msm_dsi_phy_get_shared_timings Date: Sat, 10 Jul 2021 00:07:29 +0300 Message-Id: <20210709210729.953114-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709210729.953114-1-dmitry.baryshkov@linaro.org> References: <20210709210729.953114-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Instead of fetching shared timing through an extra function call, get them directly from msm_dsi_phy_enable. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/dsi/dsi.h | 5 ++--- drivers/gpu/drm/msm/dsi/dsi_manager.c | 3 +-- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 13 +++++-------- 3 files changed, 8 insertions(+), 13 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 1f0ec78c6b05..876053ba615b 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -164,10 +164,9 @@ struct msm_dsi_phy_clk_request { void msm_dsi_phy_driver_register(void); void msm_dsi_phy_driver_unregister(void); int msm_dsi_phy_enable(struct msm_dsi_phy *phy, - struct msm_dsi_phy_clk_request *clk_req); + struct msm_dsi_phy_clk_request *clk_req, + struct msm_dsi_phy_shared_timings *shared_timings); void msm_dsi_phy_disable(struct msm_dsi_phy *phy); -void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy, - struct msm_dsi_phy_shared_timings *shared_timing); void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, enum msm_dsi_phy_usecase uc); void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 4a17f12b9316..6f90d9940e8b 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -118,8 +118,7 @@ static int enable_phy(struct msm_dsi *msm_dsi, msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req, is_dual_dsi); - ret = msm_dsi_phy_enable(msm_dsi->phy, &clk_req); - msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings); + ret = msm_dsi_phy_enable(msm_dsi->phy, &clk_req, shared_timings); return ret; } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index c76a6438ffb9..f479e37d6428 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -752,7 +752,8 @@ void __exit msm_dsi_phy_driver_unregister(void) } int msm_dsi_phy_enable(struct msm_dsi_phy *phy, - struct msm_dsi_phy_clk_request *clk_req) + struct msm_dsi_phy_clk_request *clk_req, + struct msm_dsi_phy_shared_timings *shared_timings) { struct device *dev = &phy->pdev->dev; int ret; @@ -780,6 +781,9 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, goto phy_en_fail; } + memcpy(shared_timings, &phy->timing.shared_timings, + sizeof(*shared_timings)); + /* * Resetting DSI PHY silently changes its PLL registers to reset status, * which will confuse clock driver and result in wrong output rate of @@ -819,13 +823,6 @@ void msm_dsi_phy_disable(struct msm_dsi_phy *phy) dsi_phy_disable_resource(phy); } -void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy, - struct msm_dsi_phy_shared_timings *shared_timings) -{ - memcpy(shared_timings, &phy->timing.shared_timings, - sizeof(*shared_timings)); -} - void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, enum msm_dsi_phy_usecase uc) {