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[23.128.96.18]) by mx.google.com with ESMTP id l2si2906759jak.30.2021.07.09.10.32.08; Fri, 09 Jul 2021 10:32:08 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o6PnS0Ge; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229742AbhGIReu (ORCPT + 7 others); Fri, 9 Jul 2021 13:34:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229701AbhGIReu (ORCPT ); Fri, 9 Jul 2021 13:34:50 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5966C0613E6 for ; Fri, 9 Jul 2021 10:32:06 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id f30so24737831lfj.1 for ; Fri, 09 Jul 2021 10:32:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KLWZj85HgqkOqv1HxmNCRrODidaWLC0A2DygbxwWKbA=; b=o6PnS0GeNa0e7e9IYLaOaw2dOPONtiUFh8iGm+grX09+xf9s+u3UnRFEcT+jYTQHnV WEpXItGnvRJbeiYiS7aCO9/dI09CI3C0+NkCoBvacPZeDMej5vIphi+4vrIbjDQW3xJF vDiwYl6+v2PmzA5r8Ll8sY6saB67KiDDc0VH+75xLCL6hhhU6CgckOqXCn8tPnJxQsNH o9cXFxRV83CmhIB7HXDzl9fWBd9kCfQ0DUiEJycPQ1N0sgeHMATjzVxE2p+Lb+rP+xfh 3Or7cmus14QExq/lBPH874ms5L6m2fdjG335qnw51bkqMafMN3GpK4N4OEGt8kko8aZi LJrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KLWZj85HgqkOqv1HxmNCRrODidaWLC0A2DygbxwWKbA=; b=qpigzrGpcD7XTVGlmtMFQoSXnHpQcETafhc/K8g83uDxX+AkounxUF5U4JIig7ZuPE y8IUb2fFO4R+C+37vI3AhcOSlZAHRUuF6b4o3tWUmsBx4VyB5JgSvIf7XeRL4Rzl0YlS oZt0TRn1HXbMw71Po82rVpMEYbXX+RTOFpnxNkucS/B3RwKn6Q6ClSD/Xk0X6XEh1I6f uPmw1P1ZnOtiKOy2yPSpkuQ45GDAUavmoLhtmRVgY/heUqXW8BC9UmLu+50rLW0GVT6J kvVB0eClIAWqdqgiwRWr9Ll1SKCbHGyhYkBFRmIvmrnHTq9plusqEM4fQfQ8xNV6DGBn Mypg== X-Gm-Message-State: AOAM532/78wp4PZoa8yNoYzsK97gzGTfNHo18lw6WppI/0XnFds/4tvQ fk3FbClL++rVKAvA1rIJ6uTU+g== X-Received: by 2002:a19:8c0f:: with SMTP id o15mr29897641lfd.509.1625851924989; Fri, 09 Jul 2021 10:32:04 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id b14sm511129lfb.132.2021.07.09.10.32.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 10:32:04 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v3 1/7] dt-bindings: clock: qcom, dispcc-sm8x50: add mmcx power domain Date: Fri, 9 Jul 2021 20:31:56 +0300 Message-Id: <20210709173202.667820-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709173202.667820-1-dmitry.baryshkov@linaro.org> References: <20210709173202.667820-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On sm8250 dispcc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.30.2 Reviewed-by: Bjorn Andersson diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 0cdf53f41f84..d5c4fed56b6e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -55,6 +55,11 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + required: - compatible - reg @@ -69,6 +74,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0x0af00000 0x10000>; @@ -89,5 +95,6 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; }; ...