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[23.128.96.18]) by mx.google.com with ESMTP id hb19si4810005ejc.597.2021.07.08.18.31.33; Thu, 08 Jul 2021 18:31:33 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q+7Q06TZ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230313AbhGIBdd (ORCPT + 7 others); Thu, 8 Jul 2021 21:33:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230194AbhGIBdc (ORCPT ); Thu, 8 Jul 2021 21:33:32 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13C5BC06175F for ; Thu, 8 Jul 2021 18:30:49 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id e20so5364552ljn.8 for ; Thu, 08 Jul 2021 18:30:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KLWZj85HgqkOqv1HxmNCRrODidaWLC0A2DygbxwWKbA=; b=Q+7Q06TZMaRjb0umJVm8KyLu9MHa3JJHlLCPzVZ7OBOVBMu7IhodPJTBciQftzkP27 Z9bskE9ahMvfBjG+XIf7Y/uhylwsmrCMDjm46DuoMBO+nAxF5BZbNDEYifc69xgt47aY l8uRhn4igEMAydPH4TU1JZUpHrnhC15LsuIakC1sqlCFye9ZkM+YIih3MeP1UpaAOyvv 13WBz0AFMfa8G6gk/SJx9Z0Cdu2Hqc/IbqyDI1IBWQQJ/YSR1UiQ5BkVle+FdQ3XVNR3 esK5CIfXyX9bjc9V24g9frP8cftRFEr6pTODIkXeHyeiUTVhf7duaeY9ZNMjvY/wEVwM tmJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KLWZj85HgqkOqv1HxmNCRrODidaWLC0A2DygbxwWKbA=; b=bHArHdcLvT5xyD+CRKjJk3aH7GLxwkY89pcnlxhoJdbacnqehrdv62Aw5wGlAzx+FL xNbrbk6Owo2otT+LIfYC/aWEJhXkjP4q/0x59h7vGbm7sGlERKMhoHcyoiVR1xrnSeA+ LmIfenJJpDlYmyxaNzV68r+LLaYdYse6anwiF+M223nsSMQfnPGclD0W5HlhihfTnNYp arUN/ifYmh/AGMGAtMKgcHWHXHdNUInj+dxxdMu48CyawcxasKneIcGNslHBGLwINz02 0vRqLKlWqOGhatGAuZZgXmObXkVYLljr4b53IQWBkb7ONGBhNOYsSJitl3417EkwBZbs +CUA== X-Gm-Message-State: AOAM530hN1DgG3kSBfmXHQxYiMHsFrdK/iH+7eaI8C0x6K8NYb6vDqhd sWU1gI/3v0J8DnCyr6TOZ/DZRg== X-Received: by 2002:a05:651c:d4:: with SMTP id 20mr27455105ljr.68.1625794248294; Thu, 08 Jul 2021 18:30:48 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u16sm405637ljj.113.2021.07.08.18.30.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 18:30:47 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v2 1/7] dt-bindings: clock: qcom, dispcc-sm8x50: add mmcx power domain Date: Fri, 9 Jul 2021 04:30:37 +0300 Message-Id: <20210709013043.495233-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709013043.495233-1-dmitry.baryshkov@linaro.org> References: <20210709013043.495233-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On sm8250 dispcc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 0cdf53f41f84..d5c4fed56b6e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -55,6 +55,11 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + required: - compatible - reg @@ -69,6 +74,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0x0af00000 0x10000>; @@ -89,5 +95,6 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; }; ...