From patchwork Tue Jul 6 09:56:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chun-Jie Chen X-Patchwork-Id: 470944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14C26C07E9B for ; Tue, 6 Jul 2021 09:57:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D7ECB61996 for ; Tue, 6 Jul 2021 09:56:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231338AbhGFJ7g (ORCPT ); Tue, 6 Jul 2021 05:59:36 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:46351 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231282AbhGFJ7a (ORCPT ); Tue, 6 Jul 2021 05:59:30 -0400 X-UUID: 22706eac55474611956e9b73130593d4-20210706 X-UUID: 22706eac55474611956e9b73130593d4-20210706 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 458121396; Tue, 06 Jul 2021 17:56:48 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 6 Jul 2021 17:56:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 6 Jul 2021 17:56:46 +0800 From: Chun-Jie Chen To: Matthias Brugger , Rob Herring , Nicolas Boichat CC: , , , , , , Weiyi Lu , Chun-Jie Chen Subject: [v5 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192 Date: Tue, 6 Jul 2021 17:56:14 +0800 Message-ID: <20210706095614.25603-3-chun-jie.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210706095614.25603-1-chun-jie.chen@mediatek.com> References: <20210706095614.25603-1-chun-jie.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org infra_uart0 clock is the real one what uart0 uses as bus clock. Signed-off-by: Weiyi Lu Signed-off-by: Chun-Jie Chen --- no change --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c7c7d4e017ae..9810f1d441da 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -327,7 +327,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; clock-names = "baud", "bus"; status = "disabled"; };