From patchwork Thu Jun 24 07:25:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 466485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43043C49EA7 for ; Thu, 24 Jun 2021 07:25:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D2C16100A for ; Thu, 24 Jun 2021 07:25:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231582AbhFXH2Q (ORCPT ); Thu, 24 Jun 2021 03:28:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231569AbhFXH2P (ORCPT ); Thu, 24 Jun 2021 03:28:15 -0400 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66B3CC06175F for ; Thu, 24 Jun 2021 00:25:56 -0700 (PDT) Received: by mail-pg1-x52f.google.com with SMTP id d12so3987061pgd.9 for ; Thu, 24 Jun 2021 00:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lk4v2x/QqDg9VeTcKEZY8wInplQhrFZZd/r+aGJnAFE=; b=lfu5YojMQmTHg3gKbBaPNCodpOHG+crgoh1W87Qqgd1bef2YmU+vyoXa619lt/HQWt X6tedtfe/oxIG/7AD277TrVM2HuXMC6IgFqqbvGvi3DKzF7Sz2qKkG1xVwi83VbhDkfc sgGzPrlCCOjg4+iaxz+eBQnvSP0rpf+kCyDFdXZyKLb4vKsJhOAXKUeAHHSkD2qGwQWa 9QcjVMgr2P6YeD3y1jSs7GrT0KS1BYLII/7M9IhrH9njIApm3paW4FQPvXbdiz/QUZ2c lCCRLXFE14FrmrdZMa3iMrii1B+mdoFNmMZpXRRw0yyrGv+s1h/q6hS/hmF5qrVOamnt tsoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lk4v2x/QqDg9VeTcKEZY8wInplQhrFZZd/r+aGJnAFE=; b=LUkMu1W+/fEpAJlp9uGcr0LlWfFHKEPt69N3w4yDrP/nYkKuUNOvKU8WhvQoLV4sOa 7iRvn8bUzB+RtGDHs28pTRn7IATq/MnBJaAGMf95ASPJRI5Hm07vVVKWDnxCi+rfqV6G iXGnGXWh2fbR5N62OqGuQT3kVSfS+8h+cj004R8SuW3A5Tpon9+1GThnWdCibyFqMSqW RjPWNK5ipJK/wwBu626c2W6cpddNDwBeAr6EwFpHRzCSEjPhOWp9yADVfZ8FIudVcWwT fubjwKbGkDWUQB4MsveeQ+bJb7dV7LJWh+aNCcpzXOdSjYwjH+xj/GJThDcuX7FqEbJK DC1w== X-Gm-Message-State: AOAM531B7ljpaHAxAQV7pjJ3vY2YUtcJOtL2WWHSO1lAPWL2+Ji09zWV 5Po6PcVp154WM9479X7oOiFB X-Google-Smtp-Source: ABdhPJyNgYIow+mv3H1MDcm7lN61OKCztTkl9gdR8yqK03Xqpq2UfaWpFQKOedeWDhpan1pGZcoAyA== X-Received: by 2002:a65:610c:: with SMTP id z12mr3570736pgu.453.1624519555883; Thu, 24 Jun 2021 00:25:55 -0700 (PDT) Received: from localhost.localdomain ([120.138.12.173]) by smtp.gmail.com with ESMTPSA id g13sm1923802pfv.65.2021.06.24.00.25.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 00:25:55 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh@kernel.org Cc: devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, hemantk@codeaurora.org, smohanad@codeaurora.org, bjorn.andersson@linaro.org, sallenki@codeaurora.org, skananth@codeaurora.org, vpernami@codeaurora.org, vbadigan@codeaurora.org, Manivannan Sadhasivam Subject: [PATCH v4 1/3] dt-bindings: pci: Add devicetree binding for Qualcomm PCIe EP controller Date: Thu, 24 Jun 2021 12:55:32 +0530 Message-Id: <20210624072534.21191-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210624072534.21191-1-manivannan.sadhasivam@linaro.org> References: <20210624072534.21191-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree binding for Qualcomm PCIe EP controller used in platforms like SDX55. The EP controller is based on the Designware core with Qualcomm specific wrappers. Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 160 ++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml new file mode 100644 index 000000000000..9110d33809cd --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCIe Endpoint Controller binding + +maintainers: + - Manivannan Sadhasivam + +allOf: + - $ref: "pci-ep.yaml#" + +properties: + compatible: + const: qcom,sdx55-pcie-ep + + reg: + items: + - description: Qualcomm specific PARF configuration registers + - description: Designware PCIe registers + - description: External local bus interface registers + - description: Address Translation Unit (ATU) registers + - description: Memory region used to map remote RC address space + - description: BAR memory region + + reg-names: + items: + - const: parf + - const: dbi + - const: elbi + - const: atu + - const: addr_space + - const: mmio + + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe Sleep clock + - description: PCIe Reference clock + + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: sleep + - const: ref + + qcom,perst-regs: + description: Reference to a syscon representing TCSR followed by the two + offsets within syscon for Perst enable and Perst separation + enable registers + $ref: "/schemas/types.yaml#/definitions/phandle-array" + items: + minItems: 3 + maxItems: 3 + + interrupts: + items: + - description: PCIe Global interrupt + - description: PCIe Doorbell interrupt + + interrupt-names: + items: + - const: global + - const: doorbell + + reset-gpios: + description: GPIO that is being used as PERST# input signal + maxItems: 1 + + wake-gpios: + description: GPIO that is being used as WAKE# output signal + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: core + + power-domains: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pciephy + + num-lanes: + default: 2 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - qcom,perst-regs + - interrupts + - interrupt-names + - reset-gpios + - resets + - reset-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + pcie_ep: pcie-ep@40000000 { + compatible = "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40002000 0x1000>, + <0x01c03000 0x3000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio"; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names = "aux", "cfg", "bus_master", "bus_slave", + "slave_q2a", "sleep", "ref"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + reset-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_GDSC>; + phys = <&pcie0_lane>; + phy-names = "pciephy"; + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + };