From patchwork Tue Jun 15 17:32:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 315B5C48BDF for ; Tue, 15 Jun 2021 17:33:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1685E61417 for ; Tue, 15 Jun 2021 17:33:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231398AbhFORfE (ORCPT ); Tue, 15 Jun 2021 13:35:04 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:35338 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231199AbhFORez (ORCPT ); Tue, 15 Jun 2021 13:34:55 -0400 X-UUID: 8d4b15fd808f4b959c5b70b847e000b1-20210616 X-UUID: 8d4b15fd808f4b959c5b70b847e000b1-20210616 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 336697304; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:42 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Crystal Guo Subject: [PATCH 01/27] arm64: dts: mt8195: add infracfg_rst node Date: Wed, 16 Jun 2021 01:32:08 +0800 Message-ID: <20210615173233.26682-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Crystal Guo add infracfg_rst node which is for MT8195 platform Signed-off-by: Crystal Guo --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 629cd883facf..8cda62f736b3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -8,6 +8,7 @@ #include #include +#include / { compatible = "mediatek,mt8195"; @@ -273,6 +274,20 @@ }; }; + infracfg: syscon@10001000 { + compatible = "mediatek,mt8195-infracfg", "syscon", "simple-mfd"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + + infracfg_rst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = < + 0x140 26 0x144 26 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + >; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt"; reg = <0 0x10007000 0 0x100>;