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Sat, 12 Jun 2021 16:05:35 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Rob Herring Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [RFC PATCH v1 07/10] clocksource: clint: Add support for ACLINT MTIMER device Date: Sat, 12 Jun 2021 21:34:19 +0530 Message-Id: <20210612160422.330705-8-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210612160422.330705-1-anup.patel@wdc.com> References: <20210612160422.330705-1-anup.patel@wdc.com> X-Originating-IP: [122.171.171.205] X-ClientProxiedBy: MA1PR0101CA0052.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::14) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.171.205) by MA1PR0101CA0052.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.21 via Frontend Transport; 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This patch extends the CLINT driver to support both CLINT device and ACLINT MTIMER device. Signed-off-by: Anup Patel Reviewed-by: Bin Meng --- drivers/clocksource/timer-clint.c | 43 +++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index dfdcd94c1fd5..ca329c450810 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -2,8 +2,15 @@ /* * Copyright (C) 2020 Western Digital Corporation or its affiliates. * - * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a - * CLINT MMIO timer device. + * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a CLINT + * MMIO device which is a composite device capable of injecting M-mode + * software interrupts and M-mode timer interrupts. + * + * The RISC-V ACLINT specification is modular in nature and defines + * separate devices for M-mode software interrupt (MSWI), M-mode timer + * (MTIMER) and S-mode software interrupt (SSWI). + * + * This is a common driver for CLINT device and ACLINT MTIMER device. */ #define pr_fmt(fmt) "clint: " fmt @@ -21,14 +28,20 @@ #include #include -#ifndef CONFIG_RISCV_M_MODE +#ifdef CONFIG_RISCV_M_MODE #include + +u64 __iomem *clint_time_val; +EXPORT_SYMBOL(clint_time_val); #endif #define CLINT_IPI_OFF 0 #define CLINT_TIMER_CMP_OFF 0x4000 #define CLINT_TIMER_VAL_OFF 0xbff8 +#define ACLINT_MTIMER_CMP_OFF 0x0000 +#define ACLINT_MTIMER_VAL_OFF 0x7ff8 + /* CLINT manages IPI and Timer for RISC-V M-mode */ static u32 __iomem *clint_ipi_base; static u64 __iomem *clint_timer_cmp; @@ -36,11 +49,6 @@ static u64 __iomem *clint_timer_val; static unsigned long clint_timer_freq; static unsigned int clint_timer_irq; -#ifdef CONFIG_RISCV_M_MODE -u64 __iomem *clint_time_val; -EXPORT_SYMBOL(clint_time_val); -#endif - static void clint_send_ipi(const struct cpumask *target) { unsigned int cpu; @@ -191,9 +199,15 @@ static int __init clint_timer_init_dt(struct device_node *np) return -ENODEV; } - clint_ipi_base = base + CLINT_IPI_OFF; - clint_timer_cmp = base + CLINT_TIMER_CMP_OFF; - clint_timer_val = base + CLINT_TIMER_VAL_OFF; + if (of_device_is_compatible(np, "riscv,aclint-mtimer")) { + clint_ipi_base = NULL; + clint_timer_cmp = base + ACLINT_MTIMER_CMP_OFF; + clint_timer_val = base + ACLINT_MTIMER_VAL_OFF; + } else { + clint_ipi_base = base + CLINT_IPI_OFF; + clint_timer_cmp = base + CLINT_TIMER_CMP_OFF; + clint_timer_val = base + CLINT_TIMER_VAL_OFF; + } clint_timer_freq = riscv_timebase; #ifdef CONFIG_RISCV_M_MODE @@ -230,8 +244,10 @@ static int __init clint_timer_init_dt(struct device_node *np) goto fail_free_irq; } - riscv_set_ipi_ops(&clint_ipi_ops); - clint_clear_ipi(); + if (clint_ipi_base) { + riscv_set_ipi_ops(&clint_ipi_ops); + clint_clear_ipi(); + } return 0; @@ -244,3 +260,4 @@ static int __init clint_timer_init_dt(struct device_node *np) TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt); TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt); +TIMER_OF_DECLARE(clint_timer2, "riscv,aclint-mtimer", clint_timer_init_dt);