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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id x199sm1954310oif.5.2021.06.08.14.24.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 14:24:06 -0700 (PDT) From: trix@redhat.com To: mdf@kernel.org, robh+dt@kernel.org, hao.wu@intel.com, corbet@lwn.net, fbarrat@linux.ibm.com, ajd@linux.ibm.com, bbrezillon@kernel.org, arno@natisbad.org, schalla@marvell.com, herbert@gondor.apana.org.au, davem@davemloft.net, gregkh@linuxfoundation.org, Sven.Auhagen@voleatech.de, grandmaster@al2klimov.de Cc: linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-crypto@vger.kernel.org, linux-staging@lists.linux.dev, Tom Rix Subject: [PATCH 02/11] Documentation: fpga: dfl: change FPGA indirect article to an Date: Tue, 8 Jun 2021 14:23:41 -0700 Message-Id: <20210608212350.3029742-4-trix@redhat.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210608212350.3029742-1-trix@redhat.com> References: <20210608212350.3029742-1-trix@redhat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Tom Rix Change use of 'a fpga' to 'an fpga' Signed-off-by: Tom Rix --- Documentation/fpga/dfl.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index ccc33f199df2a..ef9eec71f6f3a 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -57,7 +57,7 @@ FPGA Interface Unit (FIU) represents a standalone functional unit for the interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more descriptions on FME and Port in later sections). -Accelerated Function Unit (AFU) represents a FPGA programmable region and +Accelerated Function Unit (AFU) represents an FPGA programmable region and always connects to a FIU (e.g. a Port) as its child as illustrated above. Private Features represent sub features of the FIU and AFU. They could be @@ -311,7 +311,7 @@ The driver organization in virtualization case is illustrated below: | PCI PF Device | | | PCI VF Device | +---------------+ | +---------------+ -FPGA PCIe device driver is always loaded first once a FPGA PCIe PF or VF device +FPGA PCIe device driver is always loaded first once an FPGA PCIe PF or VF device is detected. It: * Finishes enumeration on both FPGA PCIe PF and VF device using common