From patchwork Thu Jun 3 14:22:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 453492 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA43AC47097 for ; Thu, 3 Jun 2021 14:23:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D6A3861401 for ; Thu, 3 Jun 2021 14:23:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231623AbhFCOZE (ORCPT ); Thu, 3 Jun 2021 10:25:04 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:52894 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231626AbhFCOZB (ORCPT ); Thu, 3 Jun 2021 10:25:01 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 153ENCoj097011; Thu, 3 Jun 2021 09:23:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622730192; bh=Ps9WD6JyeTZxfA3Ol9ZaQRBlCX51sSBKBNSIql3lqwA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mpfzHZw+9FwDck+d+iY6IfTa50dbuVPCHGLzoNjfeqa/U5rCunWaXHUDZTG2xzZE8 ARcQcKs/Ug6kPsZ9B9WtsVzavHM8/eujw2+96D7UbXUpf9EvCNCYxO0VD7SwUAoP+H Q+ZXYzjoke3ystOfFm4VKAKVwLFrosb0ks/lbb+A= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 153ENBTx005092 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 3 Jun 2021 09:23:12 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Thu, 3 Jun 2021 09:23:11 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Thu, 3 Jun 2021 09:23:11 -0500 Received: from a0393678-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 153EMpNI039957; Thu, 3 Jun 2021 09:23:06 -0500 From: Kishon Vijay Abraham I To: Nishanth Menon , Tero Kristo , Rob Herring CC: , , , Kishon Vijay Abraham I , Lokesh Vutla , Subject: [PATCH v4 3/5] arm64: dts: ti: k3-am642-evm: Enable PCIe and SERDES Date: Thu, 3 Jun 2021 19:52:49 +0530 Message-ID: <20210603142251.14563-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210603142251.14563-1-kishon@ti.com> References: <20210603142251.14563-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org AM642 EVM has a x4 lane PCIe connector. Enable PCIe in RC mode here. Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index dad0efa961ed..8c27f563a390 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include +#include #include #include #include @@ -466,3 +468,31 @@ &mailbox0_cluster7 { status = "disabled"; }; + +&serdes_ln_ctrl { + idle-states = ; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&pcie0_rc { + reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie0_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "disabled"; +};