From patchwork Thu Jun 3 10:38:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 453500 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CA6FC47096 for ; Thu, 3 Jun 2021 10:38:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 450FD6101B for ; Thu, 3 Jun 2021 10:38:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229747AbhFCKkM (ORCPT ); Thu, 3 Jun 2021 06:40:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229629AbhFCKkM (ORCPT ); Thu, 3 Jun 2021 06:40:12 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11243C061756 for ; Thu, 3 Jun 2021 03:38:28 -0700 (PDT) Received: by mail-pl1-x630.google.com with SMTP id q16so2651833pls.6 for ; Thu, 03 Jun 2021 03:38:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1PUdWT8u4uVKn934qZyRyKaFpSaDcuxgXKUIM2NUcww=; b=JQd0CW00L5PfyoKqy241YpEHRLDpXL7J428pHGoLWV5gL4KfpN45zGESE3IzqZl5Ps 2JIOOKC9MJyyb6LtsnE9qwCfMBkbmZiMVk/ZEPIjmE/gLqPvYM62uS37g0TpRg94m0pK yTm1pQRWAkdAKAVmOkTp2PZakbgaCUbYMbxEcTQHEM8NgKXQvhoTkrzzQGhR6xq0iiKF BQPL2FIwjZ19vcmniXY6qF7UJJo9QbK1IWshTNZoTsZiawgJoj0612tHAGBZYYXu4r71 D8YQvSgJujk6ITifGfShobCC+YmFuhROTG0O1UOuE9X7m/GRTOuiB3lVGhgnBTWPH9Ij r3pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1PUdWT8u4uVKn934qZyRyKaFpSaDcuxgXKUIM2NUcww=; b=MTe1TurIjXLcJJI1ml1KDHvno7PSa2SUPOURexCquhxt8+lF+Gq0iAexcGjP0h5nyA dug/1k4JFbHA0z6IowWdwZj7/yPiaUpka6njqPHzxXeX8PFO9aRV4a3rtv6uPDdV7gd8 nfn8JIXpl2ZxIZ2MEXLuFY/Jz7RyfJqtJeb+CgFZr/T8BTpZzkNSBjLxmWC9h0GB+Nbl a0xBw6/gDtOSAKfwe3qxcxU+QNUYQ4r8lZlIMvr2IDJHA9RyrdfbfvpbVI6U01fox6mM FR6j/RbyMPOV9nDEMedDNSKlYg3Hq/aZrU0c81sZUmQItCNKP+TiP9Wgt07KBCbpct/p AkRw== X-Gm-Message-State: AOAM531kBCbhFuiWTt7h6uELZMVSTwFuwmrUORPi97Bjbu2yepUrdTVP HBaTNA3iTgSMDmxdEndQQGPABxnYEwBt X-Google-Smtp-Source: ABdhPJxILU2zQtIZwfvk5zV2uJrCJhKVKLv/i58JTXA5joJs94szP/0rR3KDxLDg5Nxp0mI935HNIA== X-Received: by 2002:a17:902:bcc7:b029:ed:6f73:ffc4 with SMTP id o7-20020a170902bcc7b02900ed6f73ffc4mr34721411pls.1.1622716707528; Thu, 03 Jun 2021 03:38:27 -0700 (PDT) Received: from localhost.localdomain ([120.138.12.41]) by smtp.gmail.com with ESMTPSA id v67sm2053370pfb.193.2021.06.03.03.38.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 03:38:27 -0700 (PDT) From: Manivannan Sadhasivam To: lorenzo.pieralisi@arm.com, robh@kernel.org, bhelgaas@google.com Cc: bjorn.andersson@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 1/3] dt-bindings: pci: Add devicetree binding for Qualcomm PCIe EP controller Date: Thu, 3 Jun 2021 16:08:12 +0530 Message-Id: <20210603103814.95177-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210603103814.95177-1-manivannan.sadhasivam@linaro.org> References: <20210603103814.95177-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree binding for Qualcomm PCIe EP controller used in platforms like SDX55. The EP controller is based on the Designware core with Qualcomm specific wrappers. Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 144 ++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml new file mode 100644 index 000000000000..3e357cb03a5c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCIe Endpoint Controller binding + +maintainers: + - Manivannan Sadhasivam + +allOf: + - $ref: "pci-ep.yaml#" + +properties: + compatible: + const: qcom,sdx55-pcie-ep + + reg: + items: + - description: Qualcomm specific PARF configuration registers + - description: Designware PCIe registers + - description: External local bus interface registers + - description: Address Translation Unit (ATU) registers + - description: Memory region used to map remote RC address space + - description: Qualcomm specific TCSR registers + + reg-names: + items: + - const: parf + - const: dbi + - const: elbi + - const: atu + - const: addr_space + - const: tcsr + + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe Sleep clock + - description: PCIe Reference clock + + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: sleep + - const: ref + + interrupts: + maxItems: 1 + description: PCIe Global interrupt + + interrupt-names: + const: global + + reset-gpios: + description: GPIO that is being used as PERST# input signal + maxItems: 1 + + wake-gpios: + description: GPIO that is being used as WAKE# output signal + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: core + + power-domains: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pciephy + + num-lanes: + default: 2 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - reset-gpios + - resets + - reset-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + pcie_ep: pcie-ep@40000000 { + compatible = "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x42000000 0x1000>, + <0x01fcb000 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "tcsr"; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names = "aux", "cfg", "bus_master", "bus_slave", + "slave_q2a", "sleep", "ref"; + + interrupts = ; + interrupt-names = "global"; + reset-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_GDSC>; + phys = <&pcie0_lane>; + phy-names = "pciephy"; + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + };