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Sat, 22 May 2021 13:10:18 +0000 From: "Peng Fan (OSS)" To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, p.zabel@pengutronix.de, l.stach@pengutronix.de, krzk@kernel.org, agx@sigxcpu.org, marex@denx.de, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ping.bai@nxp.com, frieder.schrempf@kontron.de, aford173@gmail.com, abel.vesa@nxp.com, Peng Fan , Rob Herring Subject: [PATCH V6 1/4] dt-bindings: power: Add defines for i.MX8MM BLK-CTL power domains Date: Sat, 22 May 2021 21:42:46 +0800 Message-Id: <20210522134249.15322-2-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210522134249.15322-1-peng.fan@oss.nxp.com> References: <20210522134249.15322-1-peng.fan@oss.nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR04CA0155.apcprd04.prod.outlook.com (2603:1096:4::17) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR04CA0155.apcprd04.prod.outlook.com (2603:1096:4::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4150.23 via Frontend Transport; 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Signed-off-by: Peng Fan Reviewed-by: Frieder Schrempf Acked-by: Rob Herring --- include/dt-bindings/power/imx8mm-power.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.30.0 diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h index fc9c2e16aadc..982ca2939cdc 100644 --- a/include/dt-bindings/power/imx8mm-power.h +++ b/include/dt-bindings/power/imx8mm-power.h @@ -19,4 +19,17 @@ #define IMX8MM_POWER_DOMAIN_DISPMIX 10 #define IMX8MM_POWER_DOMAIN_MIPI 11 +#define IMX8MM_BLK_CTL_PD_VPU_G2 0 +#define IMX8MM_BLK_CTL_PD_VPU_G1 1 +#define IMX8MM_BLK_CTL_PD_VPU_H1 2 +#define IMX8MM_BLK_CTL_PD_VPU_BUS 3 +#define IMX8MM_BLK_CTL_PD_VPU_MAX 4 + +#define IMX8MM_BLK_CTL_PD_DISPMIX_CSI_BRIDGE 0 +#define IMX8MM_BLK_CTL_PD_DISPMIX_LCDIF 1 +#define IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI 2 +#define IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_CSI 3 +#define IMX8MM_BLK_CTL_PD_DISPMIX_BUS 4 +#define IMX8MM_BLK_CTL_PD_DISPMIX_MAX 5 + #endif