diff mbox series

[3/7] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl

Message ID 20210517171205.1581938-4-abelvesa@kernel.org
State New
Headers show
Series [1/7] arm64: dts: freescale: Add the top level dtsi support for imx8dxl | expand

Commit Message

Abel Vesa May 17, 2021, 5:12 p.m. UTC 
From: Abel Vesa <abel.vesa@nxp.com>

Override the I2Cs, LPUARTs, audio_ipg_clk and dma_ipg_clk with
the i.MX8DXL specific properties.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 .../boot/dts/freescale/imx8dxl-ss-adma.dtsi   | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi

Comments

Dong Aisheng May 18, 2021, 7:52 a.m. UTC | #1 
On Tue, May 18, 2021 at 1:15 AM <abelvesa@kernel.org> wrote:
>

> From: Abel Vesa <abel.vesa@nxp.com>

>

> Override the I2Cs, LPUARTs, audio_ipg_clk and dma_ipg_clk with

> the i.MX8DXL specific properties.

>

> Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>

> Signed-off-by: Jacky Bai <ping.bai@nxp.com>

> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>


Please add dt-binding update as well.
Better along with this patch series

> ---

>  .../boot/dts/freescale/imx8dxl-ss-adma.dtsi   | 53 +++++++++++++++++++

>  1 file changed, 53 insertions(+)

>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi

>

> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi

> new file mode 100644

> index 000000000000..12ccbc6587ca

> --- /dev/null

> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi

> @@ -0,0 +1,53 @@

> +// SPDX-License-Identifier: GPL-2.0+

> +/*

> + * Copyright 2019-2021 NXP

> + */

> +

> +&audio_ipg_clk {

> +       clock-frequency = <160000000>;

> +};

> +

> +&dma_ipg_clk {

> +       clock-frequency = <160000000>;

> +};

> +

> +&i2c0 {

> +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

> +       interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;

> +};

> +

> +&i2c1 {

> +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

> +       interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;

> +};

> +

> +&i2c2 {

> +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

> +       interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;

> +};

> +

> +&i2c3 {

> +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

> +       interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;

> +};

> +

> +&lpuart0 {

> +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

> +       interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;

> +};

> +

> +&lpuart1 {

> +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

> +       interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;

> +};

> +

> +&lpuart2 {

> +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

> +       interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;

> +};

> +

> +&lpuart3 {

> +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

> +       interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;

> +};

> +

> --

> 2.31.1

>

>

> _______________________________________________

> linux-arm-kernel mailing list

> linux-arm-kernel@lists.infradead.org

> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Abel Vesa June 2, 2021, 11:28 a.m. UTC | #2 
On 21-05-18 15:52:00, Dong Aisheng wrote:
> On Tue, May 18, 2021 at 1:15 AM <abelvesa@kernel.org> wrote:

> >

> > From: Abel Vesa <abel.vesa@nxp.com>

> >

> > Override the I2Cs, LPUARTs, audio_ipg_clk and dma_ipg_clk with

> > the i.MX8DXL specific properties.

> >

> > Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>

> > Signed-off-by: Jacky Bai <ping.bai@nxp.com>

> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

> 

> Please add dt-binding update as well.

> Better along with this patch series

> 


Will do in the next version.

> > ---

> >  .../boot/dts/freescale/imx8dxl-ss-adma.dtsi   | 53 +++++++++++++++++++

> >  1 file changed, 53 insertions(+)

> >  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi

> >

> > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi

> > new file mode 100644

> > index 000000000000..12ccbc6587ca

> > --- /dev/null

> > +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi

> > @@ -0,0 +1,53 @@

> > +// SPDX-License-Identifier: GPL-2.0+

> > +/*

> > + * Copyright 2019-2021 NXP

> > + */

> > +

> > +&audio_ipg_clk {

> > +       clock-frequency = <160000000>;

> > +};

> > +

> > +&dma_ipg_clk {

> > +       clock-frequency = <160000000>;

> > +};

> > +

> > +&i2c0 {

> > +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

> > +       interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;

> > +};

> > +

> > +&i2c1 {

> > +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

> > +       interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;

> > +};

> > +

> > +&i2c2 {

> > +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

> > +       interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;

> > +};

> > +

> > +&i2c3 {

> > +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

> > +       interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;

> > +};

> > +

> > +&lpuart0 {

> > +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

> > +       interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;

> > +};

> > +

> > +&lpuart1 {

> > +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

> > +       interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;

> > +};

> > +

> > +&lpuart2 {

> > +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

> > +       interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;

> > +};

> > +

> > +&lpuart3 {

> > +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

> > +       interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;

> > +};

> > +

> > --

> > 2.31.1

> >

> >

> > _______________________________________________

> > linux-arm-kernel mailing list

> > linux-arm-kernel@lists.infradead.org

> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&amp;data=04%7C01%7Cabel.vesa%40nxp.com%7Cc94d080848a648df0ad708d919d1f75f%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637569211861760914%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=J6uUG1sc6bXk2MNXKtBzH1AjIb%2FsmeXCw4Ww%2BqvrixQ%3D&amp;reserved=0
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
new file mode 100644
index 000000000000..12ccbc6587ca
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -0,0 +1,53 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+&audio_ipg_clk {
+	clock-frequency = <160000000>;
+};
+
+&dma_ipg_clk {
+	clock-frequency = <160000000>;
+};
+
+&i2c0 {
+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c1 {
+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c2 {
+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+	interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c3 {
+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart0 {
+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+	interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart1 {
+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+	interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart2 {
+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+	interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart3 {
+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+	interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+};
+