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[109.252.193.91]) by smtp.gmail.com with ESMTPSA id p6sm406478lfr.163.2021.05.16.16.18.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 May 2021 16:18:45 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , =?utf-8?q?Micha=C5=82_Miros?= =?utf-8?q?=C5=82aw?= , Rob Herring , Matt Merhar , Paul Fertser Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v5 1/3] dt-bindings: soc: tegra-pmc: Document core power domain Date: Mon, 17 May 2021 02:17:53 +0300 Message-Id: <20210516231755.24193-2-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210516231755.24193-1-digetx@gmail.com> References: <20210516231755.24193-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org All NVIDIA Tegra SoCs have a core power domain where majority of hardware blocks reside. Document the new core power domain properties. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring --- .../arm/tegra/nvidia,tegra20-pmc.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 43fd2f8927d0..0afec83cc723 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -301,6 +301,33 @@ patternProperties: additionalProperties: false + core-domain: + type: object + description: | + The vast majority of hardware blocks of Tegra SoC belong to a + Core power domain, which has a dedicated voltage rail that powers + the blocks. + + properties: + operating-points-v2: + description: + Should contain level, voltages and opp-supported-hw property. + The supported-hw is a bitfield indicating SoC speedo or process + ID mask. + + "#power-domain-cells": + const: 0 + + required: + - operating-points-v2 + - "#power-domain-cells" + + additionalProperties: false + + core-supply: + description: + Phandle to voltage regulator connected to the SoC Core power rail. + required: - compatible - reg @@ -325,6 +352,7 @@ examples: tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra210-pmc"; reg = <0x7000e400 0x400>; + core-supply = <®ulator>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; @@ -338,17 +366,24 @@ examples: nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + pd_core: core-domain { + operating-points-v2 = <&core_opp_table>; + #power-domain-cells = <0>; + }; + powergates { pd_audio: aud { clocks = <&tegra_car TEGRA210_CLK_APE>, <&tegra_car TEGRA210_CLK_APB2APE>; resets = <&tegra_car 198>; + power-domains = <&pd_core>; #power-domain-cells = <0>; }; pd_xusbss: xusba { clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + power-domains = <&pd_core>; #power-domain-cells = <0>; }; };