From patchwork Sun May 16 23:05:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 439907 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp566346jac; Sun, 16 May 2021 16:06:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz9EhIpraDQUw6dnkHGi2uFc0RkWRxyWjn2/+PmWIYwfVKyeX/X+VwJBxFjrv/O+Igw/CXz X-Received: by 2002:a02:a918:: with SMTP id n24mr53781148jam.125.1621206392349; Sun, 16 May 2021 16:06:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621206392; cv=none; d=google.com; s=arc-20160816; b=P2q3eoW/R/qbU9TPVQk2zXL79faKHnEWnDYhgrRkOqqQDDcl83yp5fpluP76rAT0AL eAL5rPtdo+vMieM5uoqbc3TCyQ0DcLvNi8RuSlKPrBq3ZzftBDLmLTZbKEa9In9Y6ISH 2t/+gIkUq6IH2QOdNm+oAshJjbEvxo2OgJhnOS9OMvwByElGBPxzjRIbXWIQOM5Avfv/ OZPgwOJvR81rS5k5Qadzdw1bCLdnkbZnLqgAywx8SYQ+tPKzs2GmGRkRT69tOZ6ZiJ3y BbfFq32TENQ/8CmKaDrclfNfaqGlxfZm/qwB5u9z73FbF2rEL/AfSCUCURBCkMHzkAX3 YG4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=QpagjBDnee6mgrVuQlrpEoBRQ+UPTqN8ipLXUovCG/Q=; b=K2oh4fDRxf+fSWtN9RmVuoZuu1Y9wlPijLfAtE0i5W9/q9oT9qfKL44axnROgoBNgr XFubB1i0x8uf+qPOXPaITPSsa/PsTVKt8KJPqU/Ic/LEG0cHjoLbkEmVoPOKGf9/I9bk 0322+4qn76WlarFnL1watkXjNhWNCwDI0u9c+HgRnqmK9UqM45DNC2spcDFomkF8Tdth fqdtfjk1nK6QU8/j8PWvmJyqqEQb7cJBY/2G734EZKWH5eMUbOoGZzeQJiFh+4oivFJY bnzsAuVAYmC6bJnpDYpXlbTLhT+phIqoAWD1cWKdBPJCO+yupKTNx6SYCP7MikCx6ks8 q6mg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x20si15268428jao.3.2021.05.16.16.06.32; Sun, 16 May 2021 16:06:32 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232508AbhEPXHk (ORCPT + 7 others); Sun, 16 May 2021 19:07:40 -0400 Received: from mx2.suse.de ([195.135.220.15]:44012 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232079AbhEPXHi (ORCPT ); Sun, 16 May 2021 19:07:38 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 04EC7B1FE; Sun, 16 May 2021 23:06:22 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Heiko Stuebner , devicetree@vger.kernel.org Subject: [PATCH 9/9] arm64: dts: rockchip: rk1808: Add CPU operating points Date: Mon, 17 May 2021 01:05:51 +0200 Message-Id: <20210516230551.12469-10-afaerber@suse.de> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210516230551.12469-1-afaerber@suse.de> References: <20210516230551.12469-1-afaerber@suse.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Associate operating points with both CPU nodes. Data source is the shipping TB-RK1808M0 DTB. Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/rockchip/rk1808.dtsi | 64 ++++++++++++++++++++++++ 1 file changed, 64 insertions(+) -- 2.31.1 diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi index b4a71c5c8be7..82614c47f144 100644 --- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi @@ -32,7 +32,10 @@ cpu0: cpu@0 { compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; + dynamic-power-coefficient = <74>; + operating-points-v2 = <&cpu0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -40,6 +43,7 @@ cpu1: cpu@1 { compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -57,6 +61,66 @@ CPU_SLEEP: cpu-sleep { }; }; + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <800000 800000 950000>; + clock-latency-ns = <40000>; + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <825000 825000 950000>; + clock-latency-ns = <40000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <850000 850000 950000>; + clock-latency-ns = <40000>; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <900000 900000 950000>; + clock-latency-ns = <40000>; + }; + }; + arm-pmu { compatible = "arm,cortex-a35-pmu"; interrupts = ,