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[23.128.96.18]) by mx.google.com with ESMTP id i23si17831905jam.97.2021.05.10.21.19.00; Mon, 10 May 2021 21:19:00 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mRuUfhiI; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230186AbhEKEUE (ORCPT + 7 others); Tue, 11 May 2021 00:20:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229586AbhEKEUD (ORCPT ); Tue, 11 May 2021 00:20:03 -0400 Received: from mail-oi1-x22f.google.com (mail-oi1-x22f.google.com [IPv6:2607:f8b0:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CA71C061574 for ; Mon, 10 May 2021 21:18:57 -0700 (PDT) Received: by mail-oi1-x22f.google.com with SMTP id x15so4118158oic.13 for ; Mon, 10 May 2021 21:18:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cIlO46CkkS5Pg+0HgvjISZiN0yDOwowrWH9c72C/51g=; b=mRuUfhiIHwmHMXwrWfnYTLt04ccW91TQ4rR5w5vnHJkszkv1a4SpShur1Uzw7r/Z8K 00uSb7n46jZxl38Rto2Onja5mznqs/0SsC2AwYvjLyCnLUprTpM7oqN3B4vUqVNtPdEx JLIMNdLQSNRI78gZM4z581JeY7JctQeygnE/CT79ZzwNHghOwl0ELV8FcacyxuHv393n 1+CCdVcjLIR7+TDymiNpBaUo6wBmkZbfmUM+eG/V8qFhJicdJhNZc5Q5tyAEIodl0vTx Zkth37mYKxMrXjKToHTDpY8emf3n2CSCzaDQPVDaxkEHPd6RSYZDjK2Pz3JN7aUUhTRv H75Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cIlO46CkkS5Pg+0HgvjISZiN0yDOwowrWH9c72C/51g=; b=Igm0OlKbiRRQQDFfO5w71nksBJtblJD9IE1+9zcRAYQOc2shfcMYZ/eaZKHdTYOTkz Q9pjJ2UfeaIJcvhibCme86EXA/g40PnKr/WxA2OLcMYT+wAR5gdgPYEzFPpVhop4KD/E Lt5SemZ+VMb+j+Dxlh7vsgzHg1ZZPBeseZYHtmEGmn/xiEark/ZCT1ZWSzqnqOM3L6CB Kj62AY/m3fftKsmrE+Cq4ZNncepEPsfa8QP40Z73uZT5r4ZLfjnQtVIf8KO5MqersKiC BuPrd+b9A0o9CALB8D3hnTHid9mylo3hdtXp6EFR7IODMGObFdtOK0OGLhC3uydi4VOq Vqkw== X-Gm-Message-State: AOAM533bNGWnb6/W4S+D4vf3CsMkEVjwx0q3Yga+HiWw0mN11zIljcNP BuURxKQ0W6U+uHFcg1nue+3dlg== X-Received: by 2002:aca:380a:: with SMTP id f10mr2031022oia.157.1620706736754; Mon, 10 May 2021 21:18:56 -0700 (PDT) Received: from localhost.localdomain ([2607:fb90:e623:42c1:10df:adff:fec2:f1d]) by smtp.gmail.com with ESMTPSA id z15sm558647otp.20.2021.05.10.21.18.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 21:18:56 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] drm/msm/dpu: Introduce knowledge of widebus feature Date: Mon, 10 May 2021 23:18:49 -0500 Message-Id: <20210511041852.592295-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210511041852.592295-1-bjorn.andersson@linaro.org> References: <20210511041852.592295-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some hardware supports clocking 2 pixels per pixel clock pulse, known as "widebus". The configuration needs to match between the DPU and the interface controller, and the timing parameters must be adjusted. As a first step towards supporting this, start by adding a INTF mask flag to signal the timing configuration code that the INTF_CONFIG2 register should be written - which will clear the bit, in the case that the bootloader left it set. Signed-off-by: Bjorn Andersson --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) -- 2.29.2 Reviewed-by: Dmitry Baryshkov diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4dfd8a20ad5c..c2f34a4f82d9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -196,12 +196,14 @@ enum { * @DPU_INTF_TE INTF block has TE configuration support * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate than video timing + * @DPU_INTF_WIDEBUS INTF block supports driving 2 pixels per clock * @DPU_INTF_MAX */ enum { DPU_INTF_INPUT_CTRL = 0x1, DPU_INTF_TE, DPU_DATA_HCTL_EN, + DPU_INTF_WIDEBUS, DPU_INTF_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 1599e3f49a4f..933485d8c03c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -183,7 +183,6 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) { intf_cfg2 |= BIT(4); display_data_hctl = display_hctl; - DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl); } @@ -204,6 +203,8 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); + if (ctx->cap->features & (BIT(DPU_DATA_HCTL_EN) | BIT(DPU_INTF_WIDEBUS))) + DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); } static void dpu_hw_intf_enable_timing_engine(