From patchwork Sat May 8 07:09:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 432669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28A42C43462 for ; Sat, 8 May 2021 07:09:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 09D5C61458 for ; Sat, 8 May 2021 07:09:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229864AbhEHHKj (ORCPT ); Sat, 8 May 2021 03:10:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229481AbhEHHKj (ORCPT ); Sat, 8 May 2021 03:10:39 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F0E2C061574 for ; Sat, 8 May 2021 00:09:37 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id m9so11388684wrx.3 for ; Sat, 08 May 2021 00:09:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cbFyM8/48A5QwY5f+jcAHfVdDdKUhqPQqn/9aWFc+bo=; b=A+9tsp1WsUbv6YGsDOBneGaswtgeo3mlJsb7bEr16UTDC+I1DyqSE8OqjVMDWlx84n INVEaYq4+1Xa3BGmNbQKDaeOVPtcchcYAoi2y6w5X9T3oT2RZd13UocYSh8vsTemka5j d6qDiwd/0mJr2P5OwdCMSStIS4N5jrA9sCpparX9N+IXxQfDxuQCBLqUmlNa5J/OQ90J vV+JaQoDW1VQTaOLqIKSK/1jgUhcuaYg1ddVdFo5pozUFuxiofpbFJTaGQqiWbYds4M3 r1mvznDuSDeccrkpmoBEcsvtcaxekcXZrFuj5d8AYtp+xdWaY4o8BPsx08XImfFprYWc G+Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cbFyM8/48A5QwY5f+jcAHfVdDdKUhqPQqn/9aWFc+bo=; b=fCbw2N+xb3m+0rBzJmnyqXMMa1QB/xNw8T4ybFUae/lczLvYLaLQ8bi+kHtKkG9NMr J6geX4tTzq3+dL7gbAgiCIuTSWytNCYS5o9UMCTRoK7ZdY+ss6HXfIdOgrmcMGiEFTwv n+J1A56xLYV5rZPXIAoL79Cf1GNJrMIyo/0SFf4I32B0apYAnqu4dC249hRAYkWMCBDU ztoMwuvTMJxzii2M63+f0XFFPX1HsJaaWD3OQdsspvrRkF0C73TSnfM4xswphrgdIOPJ AphYFI2pXDEnnzS8SpamNH9lZxit8N6xcXZ0PB3HG/5NGgyEf2LXzAm1+EC0jfxP/nWJ zBSw== X-Gm-Message-State: AOAM530DQ/lMrwNjqiFvP+YbJwpbjS1cuLKTdaHPy6crwywHalngteVr 6QJyzQf35pRgGDnVj8NGbQg= X-Google-Smtp-Source: ABdhPJxyI2ENCVd++zyUNxuNgDHuy4rRseRL4FBlKqO4/h72eQ+TmEFWLiNrBX6g0GJrm+Q8EDOY3Q== X-Received: by 2002:a5d:6087:: with SMTP id w7mr16863668wrt.136.1620457775830; Sat, 08 May 2021 00:09:35 -0700 (PDT) Received: from localhost.localdomain (231.red-83-51-243.dynamicip.rima-tde.net. [83.51.243.231]) by smtp.gmail.com with ESMTPSA id s18sm11740345wro.95.2021.05.08.00.09.34 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 May 2021 00:09:35 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: kishon@ti.com, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH RESEND v2 3/6] phy: ralink: phy-mt7621-pci: use kernel clock APIS Date: Sat, 8 May 2021 09:09:27 +0200 Message-Id: <20210508070930.5290-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508070930.5290-1-sergio.paracuellos@gmail.com> References: <20210508070930.5290-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' This allow us to properly use kernel clock apis to get the clock frequency needed for the phy configuration instead of use custom architecture code to do the same. Signed-off-by: Sergio Paracuellos --- drivers/phy/ralink/phy-mt7621-pci.c | 33 +++++++++++++++++------------ 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/phy/ralink/phy-mt7621-pci.c b/drivers/phy/ralink/phy-mt7621-pci.c index 753cb5bab930..f56ff10b0885 100644 --- a/drivers/phy/ralink/phy-mt7621-pci.c +++ b/drivers/phy/ralink/phy-mt7621-pci.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -14,8 +15,6 @@ #include #include #include -#include -#include #define RG_PE1_PIPE_REG 0x02c #define RG_PE1_PIPE_RST BIT(12) @@ -62,8 +61,6 @@ #define RG_PE1_FRC_MSTCKDIV BIT(5) -#define XTAL_MASK GENMASK(8, 6) - #define MAX_PHYS 2 /** @@ -71,6 +68,7 @@ * @dev: pointer to device * @regmap: kernel regmap pointer * @phy: pointer to the kernel PHY device + * @sys_clk: pointer to the system XTAL clock * @port_base: base register * @has_dual_port: if the phy has dual ports. * @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst' @@ -80,6 +78,7 @@ struct mt7621_pci_phy { struct device *dev; struct regmap *regmap; struct phy *phy; + struct clk *sys_clk; void __iomem *port_base; bool has_dual_port; bool bypass_pipe_rst; @@ -116,12 +115,14 @@ static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy) } } -static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) +static int mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) { struct device *dev = phy->dev; - u32 xtal_mode; + unsigned long clk_rate; - xtal_mode = FIELD_GET(XTAL_MASK, rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0)); + clk_rate = clk_get_rate(phy->sys_clk); + if (!clk_rate) + return -EINVAL; /* Set PCIe Port PHY to disable SSC */ /* Debug Xtal Type */ @@ -139,13 +140,13 @@ static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN); } - if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */ + if (clk_rate == 40000000) { /* 40MHz Xtal */ /* Set Pre-divider ratio (for host mode) */ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x01)); dev_dbg(dev, "Xtal is 40MHz\n"); - } else if (xtal_mode >= 6) { /* 25MHz Xal */ + } else if (clk_rate == 25000000) { /* 25MHz Xal */ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x00)); @@ -196,13 +197,15 @@ static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG, RG_PE1_H_PLL_BR, FIELD_PREP(RG_PE1_H_PLL_BR, 0x00)); - if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */ + if (clk_rate == 40000000) { /* 40MHz Xtal */ /* set force mode enable of da_pe1_mstckdiv */ mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG, RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV, FIELD_PREP(RG_PE1_MSTCKDIV, 0x01) | RG_PE1_FRC_MSTCKDIV); } + + return 0; } static int mt7621_pci_phy_init(struct phy *phy) @@ -212,9 +215,7 @@ static int mt7621_pci_phy_init(struct phy *phy) if (mphy->bypass_pipe_rst) mt7621_bypass_pipe_rst(mphy); - mt7621_set_phy_for_ssc(mphy); - - return 0; + return mt7621_set_phy_for_ssc(mphy); } static int mt7621_pci_phy_power_on(struct phy *phy) @@ -324,6 +325,12 @@ static int mt7621_pci_phy_probe(struct platform_device *pdev) return PTR_ERR(phy->phy); } + phy->sys_clk = devm_clk_get(dev, NULL); + if (IS_ERR(phy->sys_clk)) { + dev_err(dev, "failed to get phy clock\n"); + return PTR_ERR(phy->sys_clk); + } + phy_set_drvdata(phy->phy, phy); provider = devm_of_phy_provider_register(dev, mt7621_pcie_phy_of_xlate);