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[23.128.96.18]) by mx.google.com with ESMTP id dn20si10784617ejc.511.2021.04.26.23.54.25; Mon, 26 Apr 2021 23:54:25 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="G5H/HbjP"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234722AbhD0GzD (ORCPT + 6 others); Tue, 27 Apr 2021 02:55:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234679AbhD0GzC (ORCPT ); Tue, 27 Apr 2021 02:55:02 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B555C06175F for ; Mon, 26 Apr 2021 23:54:20 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id m11so283617pfc.11 for ; Mon, 26 Apr 2021 23:54:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TVjAMPcpFx0hHefD2s7i2zDK8kriRQm55yVj9QriI+A=; b=G5H/HbjPyGoUHgXYSN37e5Uo/+gyTai3Xh0o7gk2OuY0k/EwwsU+3NNQFK+lRz157n kl0NHZwbRHeevhmfTkg89STC7vJKQdPnNlFAd/V7eDkLDZV1cgwfp+P28q53QvCsoF3W gzU0GyZX9OxASB+M0UIQl7fLAHhpag51Kb1XjC31mawFcB3eJf9NwUWO8DIxmzXj7vxL ONbFy8tDPlgBY7GEiwH3u3J9GS7eZ6qqHMz+DwedSI7ogZ08mp6jTda01NLvxxNkPiWs sqYCY10DRZjV1BtztwzJtsXpdo3qBzLUKXjwHgHPmB4R6iDW0sCvZwjwN0Aqm1fPuo5a Ld7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TVjAMPcpFx0hHefD2s7i2zDK8kriRQm55yVj9QriI+A=; b=eNh+BDyOsTCnbV+dhuUzPcvjLfvIYO9bqjYstBdOrTERJ3hZIlnCUvquRDb2PVyRRb jzjyZAUDdvunhmCOgVh3hU8trx41QzYdBR+B4VoKL8YgtBqhiX6pyTTwTa4OFyJf8TBe L1T0o8R7fEsAe+y4VPFUSydQTB21ZyEKTzAp1nM89t52yAIx1T1rPjZ7YwPqRqh2pQRg HW9G1TNXjoSU4xvqkJAKaxdIPPmIn3T9zFHM8m2gsgyHMCeuc8k1dY6tHoh+J5lTmJNv oQt79irrN+XKMmecMDs/FH0G3nMqoBHON2ADsMnZqqHrdfuoiEFlg74hovyoplitUKWy Bvvw== X-Gm-Message-State: AOAM533g+9+6qOlykvR9E8r0J4PpIzJrBXs8H4TGR82EqTt3qKLV94pe 9yEKRoP7Od5Worz4I7JQYcFb X-Received: by 2002:a63:1a48:: with SMTP id a8mr20383191pgm.81.1619506459657; Mon, 26 Apr 2021 23:54:19 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:6d89:3c72:ece6:56fb:d9ac:583c]) by smtp.gmail.com with ESMTPSA id x22sm13391986pgx.19.2021.04.26.23.54.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Apr 2021 23:54:19 -0700 (PDT) From: Manivannan Sadhasivam To: vkoul@kernel.org, kishon@ti.com, robh+dt@kernel.org Cc: bjorn.andersson@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 2/3] phy: qcom-qmp: Use phy_status field for the status bit offset Date: Tue, 27 Apr 2021 12:23:59 +0530 Message-Id: <20210427065400.18958-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210427065400.18958-1-manivannan.sadhasivam@linaro.org> References: <20210427065400.18958-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation of the support for v4.20 PCIe PHY in SDX55, use a separate "phy_status" field for the status bit offset. This is needed because, the v4.20 PHY uses a different offset for the PHY Status. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Bjorn Andersson diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 9cdebe7f26cb..c9934b2407c4 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -2323,6 +2323,8 @@ struct qmp_phy_cfg { unsigned int start_ctrl; unsigned int pwrdn_ctrl; unsigned int mask_com_pcs_ready; + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ + unsigned int phy_status; /* true, if PHY has a separate PHY_COM control block */ bool has_phy_com_ctrl; @@ -2526,6 +2528,7 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, }; static const struct qmp_phy_cfg msm8996_pciephy_cfg = { @@ -2551,6 +2554,7 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = { .start_ctrl = PCS_START | PLL_READY_GATE_EN, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .mask_com_pcs_ready = PCS_READY, + .phy_status = PHYSTATUS, .has_phy_com_ctrl = true, .has_lane_rst = true, @@ -2580,6 +2584,7 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = { .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .no_pcs_sw_reset = true, }; @@ -2606,6 +2611,7 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, }; static const char * const ipq8074_pciephy_clk_l[] = { @@ -2638,6 +2644,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, .has_phy_com_ctrl = false, .has_lane_rst = false, @@ -2670,6 +2677,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { .start_ctrl = PCS_START | SERDES_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = 995, /* us */ @@ -2698,6 +2706,7 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { .start_ctrl = PCS_START | SERDES_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = 995, /* us */ @@ -2736,6 +2745,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { .start_ctrl = PCS_START | SERDES_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = 995, /* us */ @@ -2774,6 +2784,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { .start_ctrl = PCS_START | SERDES_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, .is_dual_lane_phy = true, .has_pwrdn_delay = true, @@ -2803,6 +2814,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -2834,6 +2846,7 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -2900,6 +2913,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -2926,6 +2940,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .is_dual_lane_phy = true, .no_pcs_sw_reset = true, @@ -2953,6 +2968,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, }; static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { @@ -2977,6 +2993,7 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .is_dual_lane_phy = true, }; @@ -3001,6 +3018,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .is_dual_lane_phy = true, }; @@ -3027,6 +3045,8 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3058,6 +3078,7 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3086,6 +3107,7 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3117,6 +3139,7 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3145,6 +3168,7 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3171,6 +3195,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .is_dual_lane_phy = true, }; @@ -3197,6 +3222,7 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3228,6 +3254,7 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3843,7 +3870,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) ready = PCS_READY; } else { status = pcs + cfg->regs[QPHY_PCS_STATUS]; - mask = PHYSTATUS; + mask = cfg->phy_status; ready = 0; }